HT46C63 データシートの表示（PDF） - Holtek Semiconductor

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HT46C63

(HT46R063B - HT46R065B) Enhanced A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R63/HT46C63

4096´15 bits, addressed by the program counter and ta-

ble pointer.

Certain locations in the program memory are reserved

for special usage:

· Location 000H

This area is reserved for program initialization. After

chip reset, the program always begins execution at lo-

cation 000H.

· Location 004H

This area is reserved for the external interrupt 0 ser-

vice program. If the INT0 input pin is activated, the in-

terrupt is enabled and the stack is not full, the program

begins execution at this location.

· Location 008H

This area is reserved for the external interrupt 1 ser-

vice program. If the INT1 input pin is activated, the in-

terrupt is enabled and the stack is not full, the program

begins execution at this location.

· Location 00CH

This area is reserved for the timer/event counter inter-

rupt service program. If a timer interrupt results from a

timer/event counter overflow, and the interrupt is en-

abled and the stack is not full, the program begins ex-

ecution at location 00CH.

· Location 010H

This area is reserved for the time base interrupt ser-

vice program. If the a time base time-out occurs, the

interrupt is enabled and the stack is not full, the pro-

gram begins execution at this location.

· Location 014H

This area is reserved for the A/D converter interrupt

service program. If the interrupt is activated (when the

A/D conversion is completed), the interrupt is enabled

and the stack is not full, the program begins execution

at this location.

· Location 018H

This area is reserved for the RTC interrupt service

program. When the RTC time-out occurs, the interrupt

is enabled and the stack is not full, the program begins

execution at this location.

· Table location

Any location in the program memory can be used as

look-up tables. The instructions ²TABRDC [m]² (the

current page, 1 page=256 words) and ²TABRDL [m]²

(the last page) transfer the contents of the lower-order

byte to the specified data memory, and the

000H

004H

008H

00C H

010H

014H

018H

D e v ic e In itia liz a tio n P r o g r a m

E x te r n a l In te r r u p t 0 S u b r o u tin e

E x te r n a l In te r r u p t 1 S u b r o u tin e

T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e

T im e B a s e T im e - o u t In te r r u p t S u b r o u tin e

A /D C o n v e r te r E O C In te r r u p t S u b r o u tin e

R T C T im e - o u t In te r r u p t s u b r o u tin e

P ro g ra m

M e m o ry

n00H

L o o k - u p T a b le ( 2 5 6 w o r d s )

nFFH

F00H

L o o k - u p T a b le ( 2 5 6 w o r d s )

FFFH

1 5 b its

N o te : n ra n g e s fro m 0 to F

Program Memory

higher-order byte to lower portion of TBLH(08H) and

the remaining bits (1 bits) of TBLH are read as ²0².

The table pointer (TBLP) is read/write register (07H),

which indicates the table location. Before accessing

the table, the location has to be placed in TBLP. The

TBLH is read only and cannot be restored. If the main

routine and the ISR(interrupt service routine) both em-

ploy the table read instruction, the contents of TBLH in

the main routine are likely to be changed by the table

read instruction used in the ISR. Errors are thus

brought about. Given this, using the table read in-

struction in the main routine and the ISR simulta-

neously should be avoided. However, if the table read

instruction has to be applied in both main routine and

the ISR, the interrupt is supposed to be disabled prior

to the table read instruction. It will not be enabled until

the TBLH in the main routine has been backup. All ta-

ble related instructions require two cycles to complete

the operation. These areas may function as normal

program memory depending upon the requirements.

Stack Register - STACK

This is a special part of memory, which is used to save

the contents of the program counter only. The stack is

organized into 8 levels and is neither part of the data not

programmable space, and is not accessible. The acti-

vated level is indexed by the stack pointer and is not ac-

Table Location

Instruction

*11 *10 *9

*8

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m]

1

1

1

1 @7 @6 @5 @4 @3 @2 @1 @0

Note: *11~*0: Table location bits

@7~@0: Table pointer bits

Table Location

P11~P8: Current program counter bits

Rev. 1.90

9

May 17, 2004

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