HT49C10-1(2007) データシートの表示（PDF） - Holtek Semiconductor

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HT49C10-1
(Rev.:2007)

LCD Type 8-Bit MCU

Holtek Semiconductor 

HT49R10A-1/HT49C10-1

Bit No.

0

1

2

3

4

5

6

7

Label

EMI

EEI

ETI

ETBI

EIF

TF

TBF

¾

Function

Control the master (global) interrupt (1=enabled; 0=disabled)

Control the external interrupt (1=enabled; 0=disabled)

Control the timer/event counter interrupt (1=enabled; 0=disabled)

Control the time base interrupt (1=enabled; 0:disabled)

External interrupt request flag (1=active; 0=inactive)

Internal timer/event counter request flag (1=active; 0=inactive)

Time base request flag (1=active; 0=inactive)

Unused bit, read as ²0²

INTC0 (0BH) Register

Bit No.

0

1~3, 5~7

4

Label

ERTI

¾

RTF

Function

Control the real time clock interrupt (1=enabled; 0:disabled)

Unused bit, read as ²0²

Real time clock request flag (1=active; 0=inactive)

INTC1 (1EH) Register

is enabled, and the stack is not full, and the TBF bit is

set, a subroutine call to location 0CH occurs. The re-

lated interrupt request flag (TBF) is reset and the EMI bit

is cleared to disable further interrupts.

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF;bit 4 of

INTC1), that is caused by a regular real time clock sig-

nal. After the interrupt is enabled, and the stack is not

full, and the RTF bit is set, a subroutine call to location

10H occurs. The related interrupt request flag (RTF) is

reset and the EMI bit is cleared to disable further inter-

rupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are all held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set both to 1 (if the stack is not

full). To return from the interrupt subroutine, ²RET² or

²RETI² may be invoked. RETI sets the EMI bit and en-

ables an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

priorities in the following table apply. These can be

masked by resetting the EMI bit.

Interrupt Source

External interrupt

Timer/event counter overflow

Time base interrupt

Real time clock interrupt

Priority

1

2

3

4

Vector

04H

08H

0CH

10H

The Timer/Event Counter interrupt request flag (TF), ex-

ternal interrupt request flag (EIF) , time base interrupt

request flag (TBF), enable Timer/Event Counter inter-

rupt bit (ETI), enable external interrupt bit (EEI) , enable

Time base interrupt bit (ETBI), and enable master inter-

rupt bit (EMI) make up of Interrupt Control register 0

(INTC0) which is located at 0BH in the RAM. The real

time clock interrupt request flag (RTF) and enable real

time clock interrupt bit (ERTI) on the other hand, consti-

tute the Interrupt Control register 1 (INTC1) which is lo-

cated at 1EH in the RAM. EMI, EEI, ETI, ETBI and ERTI

are all used to control the enable/disable status of inter-

rupts. These bits prevent the requested interrupt from

being serviced. Once the interrupt request flags (TBF,

RTF, TF and EIF) are all set, they remain in the INTC0 or

INTC1 respectively until the interrupts are serviced or

cleared by a software instruction.

It is recommended that programs do not use a ²CALL

subroutine² within the interrupt subroutine. This is be-

cause interrupts often occur in an unpredictable manner

or require to be serviced immediately in some applica-

tions. At this time, if only one stack is left, and enabling

the interrupt is not well controlled, operation of the ²call²

in the interrupt subroutine may damage the original con-

trol sequence.

Rev. 1.20

10

July 27, 2007

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