HT49C10-1(2007) データシートの表示（PDF） - Holtek Semiconductor
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HT49C10-1 Datasheet PDF : 38 Pages
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HT49R10A-1/HT49C10-1
Program Memory - ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
1024´14 bits which are addressed by the program
counter and table pointer.
Certain locations in the ROM are reserved for special
usage:
· Location 000H
Location 000H is reserved for program initialization.
After chip reset, the program always begins execution
at this location.
· Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
· Location 008H
Location 008H is reserved for the timer/event counter
interrupt service program. If a timer interrupt results
from a timer/event counter overflow, and if the inter-
rupt is enabled and the stack is not full, the program
begins execution at location 008H.
· Location 00CH
Location 00CH is reserved for the Time Base interrupt
service program. If a Time Base interrupt occurs, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 00CH.
· Location 010H
Location 010H is reserved for the real time clock inter-
rupt service program. If a real time clock interrupt oc-
curs, and the interrupt is enabled, and the stack is not
full, the program begins execution at location 010H.
· Table location
Any location in the ROM can be used as a look-up ta-
ble. The instructions ²TABRDC [m]² (the current page,
1 page=256 words) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to TBLH (Table Higher-order byte
register) (08H). Only the destination of the lower-order
byte in the table is well-defined; the other bits of the ta-
ble word are all transferred to the lower portion of
TBLH, and the remaining 2 bit is read as ²0². The
TBLH is read only, and the table pointer (TBLP) is a
read/write register (07H), indicating the table location.
Before accessing the table, the location should be
placed in TBLP. All the table related instructions re-
quire 2 cycles to complete the operation. These areas
may function as a normal ROM depending upon the
user¢s requirements.
000H
D e v ic e in itia liz a tio n p r o g r a m
004H
E x te r n a l in te r r u p t s u b r o u tin e
008H
T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e
00C H
T im e B a s e In te r r u p t
010H
R T C In te rru p t
P ro g ra m
ROM
n00H
L o o k - u p ta b le ( 2 5 6 w o r d s )
nFFH
300H
L o o k - u p ta b le ( 2 5 6 w o r d s )
3FFH
1 4 b its
N o te : n ra n g e s fro m 0 to 3
Program Memory
Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 2 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At a
commencement of a subroutine call or an interrupt ac-
knowledgment, the contents of the program counter is
pushed onto the stack. At the end of the subroutine or in-
terrupt routine, signaled by a return instruction (RET or
RETI), the contents of the program counter is restored
to its previous value from the stack. After chip reset, the
Stack Pointer will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the Stack Pointer
is decremented (by RET or RETI), the interrupt is ser-
viced. This feature prevents stack overflow, allowing the
programmer to use the structure easily. Likewise, if the
stack is full, and a ²CALL² is subsequently executed, a
stack overflow occurs and the first entry is lost (only the
most recent two return addresses are stored).
Table Location
Instruction(s)
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Note: *9~*0: Table location bits
@7~@0: Table pointer bits
Table Location
P9~P8: Current program counter bits
Rev. 1.20
7
July 27, 2007
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