HT49C30L(2012) データシートの表示（PDF） - Holtek Semiconductor
部品番号
コンポーネント説明
メーカー
HT49C30L Datasheet PDF : 41 Pages
| |||
HT49R30A-1/HT49C30-1/HT49C30L
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent four return addresses are stored).
Data Memory - RAM
The data memory (RAM) is designed with 113´8 bits,
and is divided into two functional groups, namely special
function registers and general purpose data memory,
most of which are readable/writeable, although some
are read only.
Of the two types of functional groups, the special func-
tion registers consist of an Indirect addressing register 0
(00H), a Memory pointer register 0 (MP0;01H), an Indi-
rect addressing register 1 (02H), a Memory pointer reg-
ister 1 (MP1;03H), a Bank pointer (BP;04H), an
Accumulator (ACC;05H), a Program counter
lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Real time clock control register
(RTCC;09H), a Status register (STATUS;0AH), an Inter-
rupt control register 0 (INTC0;0BH), a timer/event coun-
ter (TMR;0DH), a timer/event counter control register
(TMRC;0EH), I/O registers (PA;12H, PB;14H), and In-
terrupt control register 1 (INTC1;1EH). On the other
hand, the general purpose data memory, addressed
from 20H to 7FH, is used for data and control informa-
tion under instruction commands.
The areas in the RAM can directly handle arithmetic,
logic, increment, decrement, and rotate operations. Ex-
cept some dedicated bits, Each pin in the RAM can be
set and reset by ²SET [m].i² and ²CLR [m].i² They are
also indirectly accessible through the Memory pointer
register 0 (MP0;01H) or the Memory pointer register 1
(MP1;03H).
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1(03H) respectively. Reading lo-
cation 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
The function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 (7-bit) and MP1 (7-bit), used to access
the RAM by combining corresponding indirect address-
ing registers. MP0 can only be applied to data memory,
while MP1 can be applied to data memory and LCD dis-
play memory.
00H
In d ir e c t A d d r e s s in g R e g is te r 0
01H
M P0
02H
In d ir e c t A d d r e s s in g R e g is te r 1
03H
M P1
04H
BP
05H
ACC
06H
PCL
07H
TB LP
08H
TB LH
09H
R TC C
0A H
STATU S
0B H
IN T C 0
0C H
0D H
TM R
0E H
TM R C
0FH
10H
11H
12H
PA
13H
14H
PB
15H
16H
17H
18H
19H
1A H
1B H
1C H
1D H
1E H
IN T C 1
1FH
20H
G e n e ra l P u rp o s e
D a ta M e m o ry
(9 6 B y te s )
S p e c ia l P u r p o s e
D a ta M e m o ry
:U nused.
R e a d a s "0 "
7FH
RAM Mapping
Accumulator - ACC
The accumulator (ACC) is related to the ALU opera-
tions. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
Rev. 2.10
10
July 30, 2012
Share Link: 