HT82K68 データシートの表示（PDF） - Holtek Semiconductor

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HT82K68

Multimedia Keyboard Encoder 8-Bit MCU

Holtek Semiconductor 

HT82K68E-L/HT82K68A-L

During the execution of an interrupt subroutine, other in-

terrupt acknowledgements are held until the RETI in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine, a RET or RETI in-

struction may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced

on the latter of the two T2 pulses, if the corresponding

interrupts are enabled. In the case of simultaneous re-

quests, the following table shows the priority that is ap-

plied. These can be masked by resetting the EMI bit.

Interrupt Source

Vector

External interrupt 1

04H

Timer counter overflow

08H

Once the interrupt request flags (T0F) are set, they will

remain in the INTC register until the interrupts are ser-

viced or cleared by a software instruction.

It is suggested that a program does not use the ²CALL

subroutine² within the interrupt subroutine. Because

interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications,

if only one stack is left and enabling the interrupt is not

well controlled, once the ²CALL subroutine² operates in

the interrupt subroutine it will damage the original con-

trol sequence.

Oscillator Configuration

There are two oscillator circuits in the microcontroller.

Both are designed for system clocks; the RC oscillator

and the Crystal oscillator, which are determined by

mask options. No matter what oscillator type is

selected, the signal provides the system clock. The

HALT mode stops the system oscillator and resists the

external signal to conserve power.

If an RC oscillator is used, an external resistor between

OSC1 and VDD is needed and the resistance must

range from 20kW to 510kW. The system clock, divided

by 4, is available on OSC2, which can be used to syn-

chronize external logic. The RC oscillator provides the

most cost effective solution. However, the frequency of

the oscillation may vary with VDD, temperature and the

chip itself due to process variations. It is, therefore, not

suitable for timing sensitive operations where accurate

oscillator frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift needed for oscillator, no other external components

are needed. Instead of a crystal, the resonator can also

be connected between OSC1 and OSC2 to get a fre-

quency reference, but two external capacitors in OSC1

and OSC2 are required.

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if the

system enters the power down mode, the system clock is

stopped, but the WDT oscillator still works for a period of

approximately 78ms. The WDT oscillator can be disabled

by mask option to conserve power.

V DD

O SC1

O SC2

C r y s ta l O s c illa to r

fS Y S /4

(N M O S O p e n

D r a in O u tp u t)

System Oscillator

O SC1

O SC2

R C O s c illa to r

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or instruction clock (sys-

tem clock divided by 4), decided by mask options. This

timer is designed to prevent a software malfunction or se-

quence jumping to an unknown location with unpredict-

able results. The Watchdog Timer can be disabled by

mask option. If the Watchdog Timer is disabled, all the ex-

ecutions related to the WDT results in no operation.

Once the internal WDT oscillator (RC oscillator normally

with a period of 78ms) is selected, it is first divided by 256

(8-stages) to get the nominal time-out period of approxi-

mately 20ms. This time-out period may vary with temper-

ature, VDD and process variations. By invoking the WDT

prescaler, longer time-out periods can be realized. Writ-

ing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can

give different time-out periods. If WS2, WS1, WS0 are all

equal to 1, the division ratio is up to 1:128, and the maxi-

mum time-out period is 2.6 seconds.

S y s te m c lo c k /4

W DT

O SC

M ask

O p tio n

S e le c t

8 - b it C o u n te r

W D T P r e s c a le r

7 - b it C o u n te r

8 -to -1 M U X

W S 0~W S 2

W D T T im e - o u t

Watchdog Timer

Rev. 1.40

10

February 1, 2011

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