HT82K68 データシートの表示（PDF） - Holtek Semiconductor
部品番号
コンポーネント説明
メーカー
HT82K68 Datasheet PDF : 39 Pages
| |||
000H
D e v ic e in itia liz a tio n p r o g r a m
008H
T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e
n00H
L o o k - u p ta b le ( 2 5 6 w o r d s )
nFFH
P ro g ra m
ROM
BFFH
L o o k - u p ta b le ( 2 5 6 w o r d s )
1 6 b its
N o te : n ra n g e s fro m 0 to B
Program Memory
Certain locations in the program memory are reserved
for special usage:
· Location 000
This area is reserved for the initialization program.
After chip reset, the program always begins execution
at location 000H.
· Location 004H
Location 004H is reserved for external interrupt
service program. If the PC2 (external input pin) is
activated, the interrupt is enabled, and the stack is not
full, the program begins execution at location 004H.
The pin PE0 determine whether the rising or falling
edge of the PC2 to activate external interrupt service
program.
· Location 008H
This area is reserved for the timer counter interrupt
service program. If timer interrupt results from a timer
counter overflow, and if the interrupt is enabled and
the stack is not full, the program begins execution at
location 008H.
· Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the
current page, one page=256 words) and TABRDL [m]
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, the remaining 1 bit is read as 0. The
HT82K68E-L/HT82K68A-L
Table Higher-order byte register (TBLH) is read only.
The TBLH is read only and cannot be restored. If the
main routine and the ISR (Interrupt Service Routine)
both employ the table read instruction, the contents of
the TBLH in the main routine are likely to be changed
by the table read instruction used in the ISR. Errors
can occur. In other words, using the table read
instruction in the main routine and the ISR
simultaneously should be avoided. However, if the
table read instruction has to be applied in both the
main routine and the ISR, the interrupt is supposed to
be disabled prior to the table read instruction. It will not
be enabled until the TBLH has been backed up. The
table pointer (TBLP) is a read/write register (07H), which
indicates the table location. Before accessing the table,
the location must be placed in TBLP. All table related
instructions need 2 cycles to complete the operation.
These areas may function as normal program memory
depending upon the requirements.
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into six levels and is neither part of
the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledge-
ment, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
from the stack. After a chip reset, the SP will point to the
top of the stack.
Data Memory - RAM
The data memory is designed with 184 ´ 8 bits. It is di-
vided into two functional groups: special function regis-
ters and general purpose data memory (160´8). Most of
them are read/write, but some are read only.
The unused space before 60H is reserved for future ex-
panded usage and reading these locations will get the
result 00H. The general purpose data memory, ad-
dressed from 60H to FFH, is used for data and control
information under instruction command. All data mem-
ory areas can handle arithmetic, logic, increment, dec-
rement and rotate operations directly. Except for some
dedicated bits, each bit in the data memory can be set
Table Location
Instruction(s)
*11 *10 *9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m]
1
0
1
1 @7 @6 @5 @4 @3 @2 @1 @0
Note: *11~*0: Table location bits
@7~@0: Table location bits
P11~P8: Current program counter bits
Rev. 1.40
7
February 1, 2011
Share Link: 