HT82V26 データシートの表示（PDF） - Holtek Semiconductor
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HT82V26 Datasheet PDF : 16 Pages
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HT82V26
D8
D7
D6
D5
D4
D3
D2
D1
Set to 0 Set to 0 Set to 0 MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.
.
.
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
Note: * Power-on default value
PGA Gain Register Settings
D0
Gain
(V/V)
Gain (dB)
LSB
0*
1.0
0.0
1
1.013 0.12
.
.
.
.
.
.
0
5.43
14.7
1
5.85
15.3
Offset Registers
There are three PGA registers for use in individually programming the offset in the red, green, and blue channels. Bits
D8 through D0 control the offset range from -250mV to 250mV in 512 increments.
The coding for the offset registers is sign magnitude, with D8 as the sign bit. The Table shows the offset range as a
function of the bits D8 through D0.
D8
D7
D6
D5
D4
D3
D2
D1
D0
Offset
(mV)
MSB
LSB
0
0
0
0
0
0
0
0
0*
0
0
0
0
0
0
0
0
0
1
0.98
.
.
.
.
.
.
0
1
1
1
1
1
1
1
1
250
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
-0.98
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
-250
Note: * Power-on default value
Timing Diagrams
SD ATA
S C LK
S LO A D
R /W b A 2 A 1 A 0
tD H
tD S
tL S
D8 D7 D6 D5 D4 D3 D2 D1 D0
tL H
Serial Write Operation Timing
SD ATA
S C LK
S LO A D
R /W b A 2 A 1 A 0
tL S
D8 D7 D6 D5 D4 D3 D2 D1 D0
tR D V
tL H
Serial Read Operation Timing
Rev. 1.50
7
June 24, 2004
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