HT82V38 データシートの表示（PDF） - Holtek Semiconductor
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HT82V38 Datasheet PDF : 16 Pages
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HT82V38
Symbol
Analog Inputs
Parameter
Test Conditions
VDD Conditions
RFS
Full-scale Input Range
Vi
Input Limits
Ci
Input Capacitance
Ii
Input Current
Amplifiers
¾
¾
¾
¾
¾
¾
¾
¾
PGA Gain at Minimum
¾
¾
PGA Gain at Maximum
¾
¾
PGA Gain Resolution
¾
¾
Programmable Offset at Minimum
¾
¾
Programmable Offset at Maximum
¾
¾
Offset Resolution
¾
¾
Clamp DAC Circuit
tA
Clamp DAC resolution
¾
¾
Clamp DAC output voltage at code 0
Clamp DAC output voltage at code F
Clamp DAC Step size
Clamp DAC deviation (AVDD=3.300V)
Temperature Range
tA
Operating
Power Consumption
¾
¾
Ptot
Total Power Consumption
¾
¾
Min.
¾
AVSS-0.3
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
-50
0
¾
Typ. Max. Unit
1.6/2.0
¾
V
¾ AVDD+0.3 V
10
¾
pF
10
¾
mA
1
¾
V/V
5.85
¾
V/V
6
¾
Bits
-250
¾
mV
250
¾
mV
9
¾
Bits
4
¾
Bits
0.45
¾
V
2.7
¾
V
0.15
¾
V/Step
¾
50
mV
¾
70
°C
300
¾
mW
Timing Specification AVDD=DRVDD=3.3V, AVSS=DRVSS=0V, Ta=25°C, ADCCLK=30MHz unless otherwise stated
Symbol
Parameter
Min.
Typ.
Max.
Unit
Clock Parameters
tPRA
3-Channel Pixel Rate
tPRB
2-Channel Pixel Rate
100
¾
¾
ns
66
¾
¾
ns
tPRC
1-Channel Pixel Rate
50
¾
¾
ns
tADCLK
tC1
tC2
ADCCLK Pulse Width
CDSCLK1 Pulse Width
CDSCLK2 Pulse Width
16
¾
¾
ns
10
¾
¾
ns
10
¾
¾
ns
tC1C2
tADC2
tC2ADR
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Rising to ADCCLK Rising
0
¾
¾
ns
2
¾
¾
ns
2
¾
¾
ns
tC2ADF
CDSCLK2 Falling to ADCCLK Falling
20
¾
¾
ns
tADC1
tAD
ADCCLK Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
0
¾
¾
ns
¾
3
¾
ns
Rev. 1.00
4
July 23, 2009
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