HV9803LG-G データシートの表示（PDF） - Supertex Inc
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HV9803LG-G Datasheet PDF : 7 Pages
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HV9803
OFF Timer
In the HV9803, the timing resistor connected to RT
determines the off-time of the gate driver, and it must be
wired to GND. The equation governing the off-time of the
GATE output is given by:
TOFF = RT • 40pF
The RT input is protected from short circuit. Over-current
condition at RT inhibits the IC.
Current Sense Comparator and Timer Circuits
The function of the HV9803’s current sense comparator is
similar to that of a peak current controller. However, the GATE
pulse is not terminated immediately as the LD threshold is
met. The GATE turn off in the nth cycle is delayed by a time
T2,n determined by a timer circuit as follows:
T2,n =
1
2
•
(T1,n
+
T1,n-1)
where T1,n and T1,n-1 are the times to the LD threshold in any
two consequent switching cycles. This iterative control law is
needed for damping sub-harmonic oscillation.
Short Circuit Protection
The HV9803 is equipped with a protection comparator
having a CS threshold VLIM. When this second threshold
is triggered, the GATE output shuts off for the duration of
a restart delay, determined by the RC constant at UVLO.
The capacitor CSKIP is discharged below 200mV. A restart
delay due to charging CSKIP to the UVLO start threshold is
calculated as:
TSKIP = k • R1 • CSKIP • ln
k • VIN - 0.30V
k • VIN - 1.17V
where k = R2/(R1+R2).
Under-Voltage Shutdown
Under-voltage comparator input is provided to disable the
IC, when the UVLO input is below a threshold. Hysteresis is
provided to avoid oscillation.
Failure Modes and Effects Analysis (FMEA)
The HV9803 is designed to withstand short circuit between its
adjacent pins without damage. The following table describes
the effect of such incidental short circuit conditions.
Note, that the above control law is only valid up to a maximum
switching duty cycle Dmax= 0.8. Exceeding Dmax will cause
reduction in the LED current.
Propagation delay in the current sense comparator is one
of the most significant contributors to the LED current error.
It must be noted that the control scheme described above
does not improve this deficiency of the peak-current control
scheme by itself. Moreover, it samples the propagation delay
during T1 and replicates it during T2, essentially doubling the
error introduced by this delay. In order to eliminate this error,
the reference voltage is corrected by an auto-zero circuit. In
essence, the HV9803 samples its CS signal when the current
sense comparator triggers, detects the difference between
the sampled CS level and the reference input of the current
sense comparator. The resulting difference is subtracted
from the reference level to generate a new reference in the
next switching cycle.
GATE Output
The GATE output of the HV9803 is used to drive an external
MOSFET. It is recommended that the gate charge QG
of the external MOSFET be less than 25nC for switching
frequencies ≤100kHz and less than 15nC for switching
frequencies >100kHz.
The resulting LED current is calculated from the equation:
ILED =
0.49 • VLD - 6mV
RCS
Short Circuit
Mode
CS to VDD
Effect
The IC triggers the short circuit
protection and operates in the auto-
restart mode continuously.
VDD to GND
Short circuit across the 12V should
cause the external bias supply over-
current protection.
Should cause the external bias supply
GND to GATE over-current protection. The power
MOSFET Q1 is off.
RT to PWMD
Case 1 – PWMD = Lo: The RT pin
sources its maximum current.
GATE = 0V, and Q1 is off.
Case 2 – PWMD=Hi: The RT pin is
pulled up, shutting off the timer.
GATE is off.
PWMD to
UVLO
This will overdrive the under-voltage
threshold. However, since VIN UV
condition is harmless to the IC, there is
no effect.
UVLO to LD
LD overdrives the UVLO. If LD is lower
than the UVLO threshold, the IC shuts
off. No effect otherwise.
Doc.# DSFP-HV9803
NR012313
Supertex inc.
5
www.supertex.com
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