HWD487C データシートの表示（PDF） - Unspecified
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HWD487C Datasheet PDF : 20 Pages
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Low-Power, Slew-Rate-Limited
RS-485/RS-422 Transceivers
______________________________________________________________Pin Description
PIN
HWD481/HWD483/
HWD485/HWD487/
HWD1487
HWD488/
HWD490
DIP/SO µMAX DIP/SO µMAX
1
3
2
4
2
4
—
—
3
5
—
—
4
6
3
5
5
7
4
6
—
—
5
7
—
—
6
8
6
8
—
—
—
—
8
2
7
1
—
—
—
—
7
1
8
2
1
3
—
—
—
—
HWD489/
HWD491
NAME
NAME
DIP/SO
2
RO
3
RE
4
DE
5
6, 7
9
10
—
12
—
11
14
1, 8, 13
DI
GND
Y
Z
A
A
B
B
VCC
N.C.
FUNCTION
FUNCTION
Receiver Output: If A > B by 200mV, RO will be high;
If A < B by 200mV, RO will be low.
Receiver Output Enable. RO is enabled when RE is low; RO is
high impedance when RE is high.
Driver Output Enable. The driver outputs, Y and Z, are enabled
by bringing DE high. They are high impedance when DE is low. If
the driver outputs are enabled, the parts function as line drivers.
While they are high impedance, they function as line receivers if
RE is low.
Driver Input. A low on DI forces output Y low and output Z high.
Similarly, a high on DI forces output Y high and output Z low.
Ground
Noninverting Driver Output
Inverting Driver Output
Noninverting Receiver Input and Noninverting Driver Output
Noninverting Receiver Input
Inverting Receiver Input and Inverting Driver Output
Inverting Receiver Input
Positive Supply: 4.75V ≤ VCC ≤ 5.25V
No Connect—not internally connected
TOP VIEW
RO 1
RE 2
DE 3
DI 4
R
D
DIP/SO
B1
VCC 2
RO 3
RE 4
HWD481
HWD483
HWD485
HWD487
HWD1487
µMAX
8 VCC
7B
6A
5 GND
8A
RO 1
R
RE 2
DE 3
DI 4 D
8 VCC
7B
Rt
6
A
5 GND
HWD481
HWD483
HWD485
HWD487
HWD1487
B
Rt
DE
DI
D
A
R
RO
7 GND
RE
6 DI
5 DE
NOTE: PIN LABELS Y AND Z ON TIMING, TEST, AND WAVEFORM DIAGRAMS REFER TO PINS A AND B WHEN DE IS HIGH.
TYPICAL OPERATING CIRCUIT SHOWN WITH DIP/SO PACKAGE.
Figure 1. HWD481/HWD483/HWD485/HWD487/HWD1487 Pin Configuration and Typical Operating Circuit
7
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