HX6256
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Symbol
TAVAVW
Parameter
Write Cycle Time
Typical (2)
13
Worst Case (3)
Min
Max
25
Units
ns
TWLWH
Write Enable Write Pulse Width
9
20
ns
TSLWH
Chip Select to End of Write Time
10
20
ns
TDVWH
Data Valid to End of Write Time
5
15
ns
TAVWH
Address Valid to End of Write Time
9
20
ns
TWHDX
Data Hold Time after End of Write Time
0
0
ns
TAVWL
Address Valid Setup to Start of Write Time
0
0
ns
TWHAX
Address Valid Hold after End of Write Time
0
0
ns
TWLQZ
Write Enable to Output Disable Time
3
0
9
ns
TWHQX
Write Disable to Output Enable Time
9
5
ns
TWHWL
Write Disable to Write Enable Pulse Width (5)
4
5
ns
TEHWH
Chip Enable to End of Write Time (6)
12
20
ns
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V,
input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or
equivalent capacitive load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
(4) TAVAV = TWLWH + TWHWL
(5) Guaranteed but not tested.
(6) Chip Enable (CE) pin not available on 28-lead FP or DIP.
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