HY57V641620HG データシートの表示（PDF） - Hynix Semiconductor

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HY57V641620HG

4 Banks x 1M x 16Bit Synchronous DRAM

Hynix Semiconductor 

HY57V641620HG

4 Banks x 1M x 16Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.

HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

• Single 3.3±0.3V power supply Note)

• All device pins are compatible with LVTTL interface

• JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

• All inputs and outputs referenced to positive edge of

system clock

• Data mask function by UDQM or LDQM

• Internal four banks operation

ORDERING INFORMATION

• Auto refresh and self refresh

• 4096 refresh cycles / 64ms

• Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

• Programmable CAS Latency ; 2, 3 Clocks

Part No.

HY57V641620HGT-5/55/6/7

HY57V641620HGT-K

HY57V641620HGT-H

HY57V641620HGT-8

HY57V641620HGT-P

HY57V641620HGT-S

HY57V641620HGLT-5/55/6/7

HY57V641620HGLT-K

HY57V641620HGLT-H

HY57V641620HGLT-8

HY57V641620HGLT-P

HY57V641620HGLT-S

Clock Frequency

200/183/166/143MHz

133MHz

133MHz

125MHz

100MHz

100MHz

200/183/166/143MHz

133MHz

133MHz

125MHz

100MHz

100MHz

Power

Normal

Low power

Organization

4Banks x 1Mbits

x16

Interface

LVTTL

Package

400mil 54pin TSOP II

Note : VDD(Min) of HY57V641620HG(L)T-5/55/6 is 3.135V

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use

of circuits described. No patent licenses are implied.

Rev. 0.8/Dec. 02

1

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