1893CF データシートの表示（PDF） - Integrated Device Technology

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1893CF

3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

Integrated Device Technology 

ICS1893CF Data Sheet Rev. J - Release

Chapter 4 Operating Modes Overview

4.1.2 Specific Reset Operations

This section discusses the following specific ways that the ICS1893CF can be reset:

• Hardware reset (using the RESETn pin)

• Power-on reset (applying power to the ICS1893CF)

• Software reset (using Control Register bit 0.15)

Note: At the completion of a reset (either hardware, power-on, or software), the ICS1893CF sets all

registers to their default values.

4.1.2.1 Hardware Reset

Entering Hardware Reset

Holding the active-low RESETn pin low for a minimum of five REF_IN clock cycles initiates a hardware

reset (that is, the ICS1893CF enters the reset state). During reset, the ICS1893CF executes the steps

listed in Section 4.1.1.1, “Entering Reset”.

Exiting Hardware Reset

After the signal on the RESETn pin transitions from a low to a high state, the ICS1893CF completes in 640

ns (that is, in 16 REF_IN clocks) steps 1 through 5, listed in Section 4.1.1.2, “Exiting Reset”. After the first

five steps are completed, the Serial Management Port is ready for normal operations, but this action does

not signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and

receive clock (RXCLK) are available, which is typically 53 ms after the RESETn pin goes high. [For details

on this transition, see Section 9.5.16, “Reset: Hardware Reset and Power-Down”.]

Note:

1. The MAC Interface is not available for use until the TXCLK and RXCLK are valid.

2. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit

that is used to initiate a software reset.

4.1.2.2 Power-On Reset

Entering Power-On Reset

When power is applied to the ICS1893CF, it waits until the potential between VDD and VSS achieves a

minimum voltage before entering reset and executing the steps listed in Section 4.1.1.1, “Entering Reset”.

After entering reset from a power-on condition, the ICS1893CF remains in reset for approximately 20 µs.

(For details on this transition, see Section 9.5.15, “Reset: Power-On Reset”.)

Exiting Power-On Reset

The ICS1893CF automatically exits reset and performs the same steps as for a hardware reset. (See

Section 4.1.1.2, “Exiting Reset”.)

Note: The only difference between a hardware reset and a power-on reset is that during a power-on

reset, the ICS1893CF isolates its RESETn input pin. All other functionality is the same. As with a

hardware reset, Control Register bit 0.15 does not represent the status of a power-on reset.

ICS1893CF, Rev. J, 08/11/09

Copyright © 2009, Integrated Device Technology, Inc.

All rights reserved.

11

August, 2009

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