307G-03LF データシートの表示（PDF） - Integrated Circuit Systems
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307G-03LF Datasheet PDF : 12 Pages
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ICS307-03
SERIALLY PROGRAMMABLE CLOCK SOURCE
Programming Interface
The dynamic register within the ICS307-03 controls the entire device and may be reprogrammed any time
after power is properly applied. If V or R values are changed, the frequency will transition smoothly to the
new value without glitches or short cycles. However, changing any divider or mux in the output signal path
may generate a glitch.
The register is 132 bits in length and accepts the MSB first. The SCLK signal latches the current data bit
value in the rising edge of It latches the most recently shifted 132 bit values into the control register of
device whenever CS is high. Care must be taken to ensure that CS is always low until the system is ready
to load in a new register value and that SCLK is never toggled high when CS is high.
The register can be programmed any time after power is applied, even while in power-down (pin 15 or bit
112 held low) with the waveform and timing shown below:.
Figure 2: ICS307-03 Programming Timing Diagram
DIN
131
130
129 128
tsetup
thold
2
1
0
SCLK
CS
tw
ts
Table 8: AC Parameters for Programming the ICS307-03
Parameter
tSETUP
tHOLD
tW
tS
Condition
Setup time
Hold time after SCLK
Data wait time
Strobe pulse width
SCLK Frequency
Min.
Max.
Units
2.5
ns
2.5
ns
2.5
ns
10
ns
200
MHz
Programming with VersaClock Software
The VersaClock II Software not only generates the programming word for the user, it can also be used to program
the device via the host computer’s parallel port. Demonstration boards are available from ICS that allows the
VersaClock II S/W to directly connect the ICS307-03 to a Windows based PC’s DB-25 parallel port connector and
programmed simply by pressing the “Program Part” button.
Contact ics-mk@icst.com for more details.
MDS 307-03 C
9
Revision 101705
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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