ICS8343I データシートの表示（PDF） - Integrated Circuit Systems
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ICS8343I Datasheet PDF : 14 Pages
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Integrated
Circuit
Systems, Inc.
ICS8343I
LOW SKEW, 1-TO-16
LVCMOS LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 3
4, 5
6, 7, 8,
17, 18, 19
VDD1
Q3, Q4
GND
Power
Output
Power
Output Q0 thru Q7 power supply.
Clock outputs. 14Ω typical output impedance.
LVCMOS/LVTTL interface levels.
Power supply ground.
9, 10, 11 Q5, Q6, Q7 Output
Clock outputs. 14Ω typical output impedance.
12
CLK
Input
Clock input. LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL interface levels.
13
14, 15, 16
VDD
Q8, Q9, Q10
20, 21
Q11, Q12
Power
Output
Output
Positive supply pin.
Clock outputs. 14Ω typical output impedance.
LVCMOS/LVTTL interface levels.
Clock outputs. 14Ω typical output impedance.
LVCMOS/LVTTL interface levels.
22, 23, 24
VDD2
25, 26, 27 Q13, Q14, Q15
Power
Output
28
OE2
Input
29
OE1
Input
30, 31, 32 Q0, Q1, Q2 Output
Pullup
Pullup
Output Q8 thru Q15 power supply.
Clock outputs. 14Ω typical output impedance.
LVCMOS/LVTTL interface levels.
Output enable. When low forces outputs Q8 thru Q15 to HiZ state.
LVCMOS/LVTTL interface levels.
Output enable. When low forces outputs Q0 thru Q7 to HiZ state.
LVCMOS/LVTTL interface levels.
Clock outputs. 14Ω typical output impedance.
LVCMOS/LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
Test Conditions
VDD1, VDD2 = 5.25V
VDD1, VDD2 = 3.47V
VDD1, VDD2 = 2.63V
Minimum
Typical
15
11
9.5
Maximum
Units
pF
pF
pF
pF
TABLE 3. FUNCTION TABLE
OE1
0
1
0
1
Inputs
OE2
0
0
1
1
Outputs
Q0:Q7
Q8:Q15
Hi Z
Hi Z
Active
Hi Z
Hi Z
Active
Active
Active
8343YI
www.icst.com/products/hiperclocks.htlml
2
REV. D SEPTEMBER 17, 2002
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