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ICS84325 データシートの表示(PDF) - Integrated Circuit Systems

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ICS84325 Datasheet PDF : 15 Pages
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Integrated
Circuit
Systems, Inc.
ICS84325
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84325 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 24resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
VCC
VCCA
3.3V
.01µF 24
.01µF
10 µF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Zo = 50
FOUT
FIN
Zo = 50
50
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
Zo
50
VCC - 2V
RTT
FOUT
3.3V
125
125
Zo = 50
FIN
Zo = 50
84
84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
84325EM
www.icst.com/products/hiperclocks.html
7
REV. B OCTOBER 11, 2004

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