ICS85301 データシートの表示（PDF） - Integrated Circuit Systems

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ICS85301

2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS85301

2:1

DIFFERENTIAL-TO-LVPECL MULTIPLEXER

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1

PCLK0 Input Pulldown Non-inverting differential LVPECL clock input.

2

nPCLK0

Input

Pullup/

Pulldown

Inverting differential LVPECL clock input. VCC/2 default when left floating.

3

PCLK1 Input Pulldown Non-inverting differential LVPECL clock input.

4

5

7, 16

nPCLK1

VBB

nc

Input

Output

Unused

Pullup/

Pulldown

Inverting differential LVPECL clock input. VCC/2 default when left floating.

Bias voltage.

No connect.

Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.

6

CLK_SEL Input Pulldown When LOW, selects PCLK0, nPCLK0 inputs.

LVCMOS / LVTTL interface levels.

8, 13

9, 12, 14, 15

10, 11

VCC

VEE

nQ, Q

Power

Power

Output

Positive supply pins.

Negative supply pins.

Differential output pair. LVPECL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

CIN

RPULLUP

RPULLDOWN

Parameter

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

Test Conditions

Minimum

Typical

1

37

37

Maximum

Units

pF

kΩ

kΩ

TABLE 3. CONTROL INPUT FUNCTION TABLE

Input

CLK_SEL

0

1

Input Selected

PCLK

PCLK0, nPCLK0

PCLK1, nPCLK1

85301AK

www.icst.com/products/hiperclocks.html

2

REV. A JANUARY 16, 2006

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