ICS87004AG データシートの表示（PDF） - Integrated Circuit Systems
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ICS87004AG Datasheet PDF : 14 Pages
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Integrated
Circuit
Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 12, 21
GND
Power
Power supply ground.
2, 20, 22, 24
Q0, Q3,
Q2, Q1
Output
Clock outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
3, 19, 23
4, 5, 6, 7
8
VDDO
SEL0, SEL1,
SEL2, SEL3
CLK_SEL
Power
Input
Input
Pulldown
Pulldown
Output supply pins.
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects differential CLK1, nCLK1.
When LOW, selects differential CLK0, nCLK0.
LVCMOS/LVTTL interface levels.
9
VDD
Power
Core supply pin.
10
CLK0
Input Pulldown Non-inverting differential clock input.
11
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
13
VDDA
Power
Analog supply pin.
14
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
15
CLK1
Input Pulldown Non-inverting differential clock input.
Selects between the PLL and reference clock as input to the dividers.
16
PLL_SEL Input Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL feedback input to phase detector for regenerating
17
FB_IN
Input Pulldown clocks with "zero delay". Connect to one of the outputs.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
18
MR
Input Pulldown reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
CPD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
R
OUT
Output Impedance
Test Conditions
VDD, VDDA, VDDO = 3.465V
VDD, VDDA, VDDO = 2.625V
Minimum
5
Typical
4
51
51
7
Maximum
23
17
12
Units
pF
KΩ
KΩ
pF
pF
Ω
87004AG
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 16, 2004
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