ICS87004AG データシートの表示（PDF） - Integrated Circuit Systems
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ICS87004AG Datasheet PDF : 14 Pages
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Integrated
Circuit
Systems, Inc.
ICS87004
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
TABLE 3A. PLL ENABLE FUNCTION TABLE
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Inputs
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference Frequency Range (MHz)
125 - 250
62.5 - 125
31.25 - 62.5
15.625 -31.25
125 - 250
62.5 - 125
31.25 - 62.5
125 - 250
62.5 - 125
125 - 250
62.5 - 125
31.25 - 62.5
15.625 - 31.25
31.25 - 62.5
15.625 - 31.25
15.625 - 31.25
Outputs
PLL_SEL = 1
PLL Enable Mode
Q0:Q3
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
TABLE 3B. PLL BYPASS FUNCTION TABLE
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
87004AG
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Inputs
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
www.icst.com/products/hiperclocks.html
3
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q0:Q3
÷8
÷8
÷8
÷ 16
÷ 16
÷ 16
÷ 32
÷ 32
÷ 64
÷ 128
÷4
÷4
÷8
÷2
÷4
÷2
REV. A JUNE 16, 2004
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