AV9248-73 データシートの表示（PDF） - Integrated Circuit Systems

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AV9248-73

Frequency Timing Generator for Pentium II Systems

Integrated Circuit Systems 

ICS9248 - 73

Absolute Maximum Ratings

Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6V

I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

Input Low Current

Operating Supply

Current

VIH

2

VDD+0.3 V

VIL

VSS-0.3

0.8

V

IIH

VIN = VDD

0.1

5

µA

IIL1

VIN = 0 V; Inputs with no pull-up resistors

-5 2.0

µA

IIL2

VIN = 0 V; Inputs with pull-up resistors

-200 -100

µA

IDD3.3OP66 Select @ 66MHz; Max discrete cap loads

IDD3.3OP100 Select @ 100MHz; Max discrete cap loads

300

380 mA

300

IDD2.5OP66 Select @ 66MHz; Max discrete cap loads

IDD2.5OP100 Select @ 100MHz; Max discrete cap loads

14

70

mA

21 100

Power Down

Supply Current

IDD3.3PD CL = 0 pF; PWRDWN# = 0

5

10 mA

Input frequency

Input Capacitance1

Fi

VDD = 3.3 V

CIN Logic Inputs

Transition Time1

Settling Time1

Clk Stabilization1

CINX

TTrans

TS

TStab

X1 & X2 pins

To 1st crossing of target Freq.

From 1st crossing to 1% target Freq.

From VDD = 3.3 V to 1% target Freq.

Delay

tPZH, tPZH Output enable delay (all outputs)

tPLZ, tPZH Output diable delay (all outputs)

1Guaranteed by design, not 100% tested in production.

12 14.318 16

5

27

36

45

3

1

3

3

1

10

1

10

MHz

pF

pF

ms

ms

ms

ns

ns

6

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