IDT49FCT806/A データシートの表示（PDF） - Integrated Device Technology

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IDT49FCT806/A

FAST CMOS BUFFER/CLOCK DRIVER

Integrated Device Technology 

IDT49FCT806/A

FAST CMOS BUFFER/CLOCK DRIVER

TEST CIRCUITS AND WAVEFORMS

VCC

7V

VIN

P u lse

G e n e ra to r

500

VOUT

D.U.T.

50pF

RT

500

CL

Test Circuits for All Outputs

COMMERCIAL TEMPERATURE RANGE

SWITCH POSITION

Test

Disable LOW

Enable LOW

Disable HIGH

Enable HIGH

Switch

Closed

GND

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

IN PUT

OUTPUT

IN PU T

OUTPUT

tP L H

tPHL

tR

Package Delay

tF

3V

1 .5 V

0V

VOH

2.0V

1.5V

0.8V

VOL

tPLH

tPHL

tSK(p) = tPHL - tPLH

Pulse Skew - tSK(P)

3V

1.5V

0V

VOH

1 .5 V

VOL

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

ENABLE

tP Z L

SW ITCH

CLOSED

tP Z H

3 .5 V

1.5V

SW ITCH

OPEN

1.5V

0V

D ISABLE

tPLZ

3V

1.5V

0V

tPHZ

3.5V

0.3V VOL

0.3V VOH

0V

Enable and Disable Times

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH

2. Pulse Generator for All Pulses: Rate ≤1.0MHz; tF ≤2.5ns; tR ≤2.5ns

IN PUT

OUTPUT 1

OUTPUT 2

tP LH 1

tP LH 1

tS K (o )

tS K (o )

tP L H 2

tP H L 2

tSK(o) = tPLH2 - tPLH1 or tPHL2 - tPHL1

Output Skew

3V

1 .5 V

0V

VOH

1 .5 V

VOL

VOH

1 .5 V

VOL

INPU T

PACKAGE 1

OUTPUT

PACKAGE 2

OUTPUT

tP L H 1

tPHL1

tS K (p p )

tS K (p p )

tP LH 2

tPHL2

tSK(pp) = tPLH2 - tPLH1 or tPHL2 - tPHL1

3V

1.5V

0V

VOH

1.5V

VOL

VOH

1.5V

VOL

Part-to-Part Skew - tSK(PP)

NOTE:

1. Package 1 and Package 2 are same device type and speed grade.

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