IDT54FCT16646ET データシートの表示（PDF） - Integrated Device Technology

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IDT54FCT16646ET

FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTERS (3-STATE)

Integrated Device Technology 

IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET

FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

FCT16646T/162646T

Com'l.

Mil.

Symbol

Parameter

Condition(1)

Min.(2) Max. Min.(2) Max.

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tPLH

tPHL

tPLH

tPHL

tSU

tH

tW

tSK(o)

Propagation Delay

Bus to Bus

Output Enable Time

xDIR or xOE to Bus

Output Disable Time

xDIR or xOE to Bus

Propagation Delay

Clock to Bus

Propagation Delay

xSBA or xSAB to Bus

Set-up Time HIGH or

LOW Bus to Clock

Hold Time HIGH or

LOW Bus to Clock

Clock Pulse Width

HIGH or LOW

Output Skew(3)

CL = 50pF

RL = 500Ω

2.0 9.0 2.0 11.0

2.0 14.0 2.0 15.0

2.0 9.0 2.0 11.0

2.0 9.0 2.0 10.0

2.0 11.0 2.0 12.0

4.0

—

4.5

—

2.0

—

2.0

—

6.0

—

6.0

—

—

0.5

—

0.5

FCT16646AT/162646AT

Com'l.

Mil.

Min.(2) Max. Min.(2) Max. Unit

2.0 6.3 2.0 7.7 ns

2.0 9.8 2.0 10.5 ns

2.0 6.3 2.0 7.7 ns

2.0 6.3 2.0 7.0 ns

2.0 7.7 2.0 8.4 ns

2.0

—

2.0

— ns

1.5

—

1.5

— ns

5.0

—

5.0

— ns

—

0.5

—

0.5 ns

2540 tbl 09

FCT16646CT/162646CT

FCT16646ET/162646ET

Com'l.

Mil.

Com'l.

Mil.

Symbol

Parameter

Condition(1)

Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tPLH

tPHL

tPLH

tPHL

tSU

tH

tW

tSK(o)

Propagation Delay

Bus to Bus

Output Enable Time

xDIR or xOE to Bus

Output Disable Time

xDIR or xOE to Bus

Propagation Delay

Clock to Bus

Propagation Delay

xSBA or xSAB to Bus

Set-up Time HIGH or

LOW Bus to Clock

Hold Time HIGH or

LOW Bus to Clock

Clock Pulse Width

HIGH or LOW

Output Skew(3)

CL = 50pF

1.5 5.4 1.5 6.0 1.5 3.8

—

— ns

RL = 500Ω

1.5 7.8 1.5 8.9 1.5 4.8

—

— ns

1.5 6.3 1.5 7.7 1.5 4.0

—

— ns

1.5 5.7 1.5 6.3 1.5 3.8

—

— ns

1.5 6.2 1.5 7.0 1.5 4.2

—

— ns

2.0

—

2.0

—

2.0

—

—

— ns

1.5

—

1.5

—

0.0

—

—

— ns

5.0

—

5.0

—

3.0(4)

—

—

— ns

—

0.5

—

0.5

—

0.5

—

— ns

NOTES:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

4. This limit is guaranteed but not tested.

2540 tbl10

5.13

7

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