IDT54FCT841DTLB データシートの表示（PDF） - Integrated Device Technology
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IDT54FCT841DTLB Datasheet PDF : 7 Pages
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IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
PIN CONFIGURATIONS
OE 1
24 VCC
D0 2
23 Y0
D1 3
22 Y1
D2 4 P24-1 21 Y2
D3 5 D24-1 20 Y3
D4
D5
6
7
SO24-2
SO24-7
19
18
Y4
Y5
D6
8
SO24-8
&
17
Y6
D7 9 E24-1 16 Y7
D8 10
15 Y8
D9 11
GND 12
14 Y9
13 LE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
D2
4
5
3
2
1
28 27 26
25
Y2
D3 6
24 Y3
D4 7
23 Y4
NC 8
D5 9
L28-1
22 NC
21 Y5
D6 10
20 Y6
D7 11
19 Y7
1213 14 15 16 17 18
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
2571 drw 02
LCC
TOP VIEW
2571 drw 03
PIN DESCRIPTION
FUNCTION TABLE(1)
Name
DI
I/O
Description
I
The latch data inputs.
LE
I
The latch enable input. The latches are
transparent when LE is HIGH. Input data
is latched on the HIGH-to-LOW
transition.
YI
O The 3-state latch outputs.
OE
I
The output enable control. When OE is
LOW, the outputs are enabled. When OE
is HIGH, the outputs VI are in high-
impedance (off) state.
2571 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial Military Unit
VTERM(2) Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
–0.5 to
VCC +0.5
–0.5 to
V
VCC +0.5
TA
Operating
0 to +70 –55 to +125 °C
Temperature
TBIAS Temperature
–55 to +125 –65 to +135 °C
Under Bias
TSTG Storage
–55 to +125 –65 to +150 °C
Temperature
PT
Power Dissipation
0.5
0.5
W
IOUT
DC Output
–60 to +120 –60 to +120 mA
Current
NOTES:
2571 lnk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
Inputs
OE
LE
Internal Output
DI
QI
YI
Function
H
H
L
L
Z High Z
H
H
H
H
Z High Z
H
L
X
NC
Z Latched (High Z)
L
H
L
L
L Transparent
L
H
H
H
H Transparent
L
L
X
NC
NC Latched
NOTE:
2571 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, Z = High Impedance
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN
Input
VIN = 0V
6
10 pF
Capacitance
COUT Output
VOUT = 0V 8
12 pF
Capacitance
NOTE:
2571 lnk 04
1. This parameter is measured at characterization but not tested.
6.22
2
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