IDT5V2528 データシートの表示（PDF） - Integrated Device Technology
部品番号
コンポーネント説明
メーカー
IDT5V2528 Datasheet PDF : 7 Pages
| |||
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Terminal
Name
No.
CLK(1)
6
Type Description
I
Clock input
FBIN
7
G_Ctrl(2)
28
I
3-level
Feedback input
3-level input for 2.5V / 3.3V Output Select/ Output bank enable. When G_Ctrl is LOW, all outputs except FBOUT are disabled
to a logic-LOW state. When G_Ctrl is MID or HIGH, all outputs are enabled and switch at the same frequency as CLK (see
OUTPUT SELECTION table).
T_Ctrl(2)
1
3-level 3-level input for 2.5V / 3.3V Output Select (see OUTPUT SELECTION table)
FBOUT
22
O
Feedback output
TY(7:0) 3, 10, 12, 13,
O
16, 17, 24, 26
2.5V or 3.3V Clock outputs. 1, 2, 3, 5, or 7 of these outputs may be selected as 2.5V outputs (see OUTPUT SELECTION table).
Y (1:0)
AVDD(3)
AGND
19, 20
5
8
O
Power
Ground
3.3V Clock Outputs
3.3V Analog power supply. AVDD provides the power reference for the analog circuitry.
Analog ground. AGND provides the ground reference for the analog circuitry.
VDD
21
Power 3.3V Power supply
VDDQ 4, 11, 15, 25 Power 2.5V or 3.3V Power supply for TY outputs
GND 2, 9, 14, 18 Ground Ground
23, 27
NOTES:
1. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time of 1ms
is required for the PLL to phase lock the feedback signal to the reference signal.
2. 3-level inputs will float to MID logic level if left unconnected.
3. AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the outputs.
STATIC FUNCTION TABLE (AVDD = 0V)(1)
Inputs
Outputs
G_Ctrl T_Ctrl
CLK
TY(7:0)
Y(1:0)
FBOUT
L
X
L
L
L
L
L
X
H
L
L
H
see
H
H
H
H
OUTPUT SELECTION
L
L
L
L
table
running
running running
running
NOTE:
1. AVDD should be powered up along with VDD, before setting AVDD to ground, to put the
control pins in a valid state.
OUTPUT SELECTION
G_Ctrl
M
M
M
H
H
H
T_Ctrl
L
M
H
L
M
H
TY(7:0)
TY0 (2.5V)
TY1 - TY7 (3.3V)
TY1, TY2 (2.5V)
TY0, TY3 - TY7 (3.3V)
TY0 - TY2 (2.5V)
TY3 - TY7 (3.3V)
TY0 - TY4 (2.5V)
TY5 - TY7 (3.3V)
TY1 - TY7 (2.5V)
TY0 (3.3V)
TYo - TY7 (3.3V)
VDDQ
Configuration
Pin 4 (2.5V)
Pins 11, 15, 25 (3.3V)
Pin 25 (2.5V)
Pins 4, 11, 15 (3.3V)
Pins 4, 25 (2.5V)
Pins 11, 15 (3.3V)
Pins 4, 15, 25 (2.5V)
Pin 11 (3.3V)
Pins 11, 15, 25 (2.5V)
Pin 4 (3.3V)
Pins 4, 11, 15, 25 (3.3V)
DYNAMIC FUNCTION TABLE (AVDD = 3.3V)
Inputs
Outputs
G_Ctrl T_Ctrl
CLK
TY(7:0)
Y(1:0)
FBOUT
L
X
L
L
L
L
L
X
H
L
L
H
see OUTPUT
L
L
L
L
SELECTION table
H
H
H
H
3
Share Link: 