IDT5V2528 データシートの表示（PDF） - Integrated Device Technology
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IDT5V2528 Datasheet PDF : 7 Pages
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IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS OVER OPERATING RANGE
5V2528
5V2528A
Min
Max
Min
Max
Units
fCLOCK
Clock frequency
25
140
25
167
MHz
Input clock duty cycle
40%
60%
40%
60%
tLOCK
Stabilization time(1)
1
1
ms
NOTE:
1.Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference
signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are
not applicable.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 5V2528(1)
Symbol
Parameter(2)
Min.
tPHASE error
Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-133MHz)
–150
tPHASEerror-jitter(3) Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (133MHz)
–50
tSK1(0)(4)
Output Skew between 3.3V Outputs
—
tSK2(0)(4)
Output Skew between 2.5V Outputs
—
tSK3(0)(4,5)
Output Skew between 2.5V and 3.3V Outputs
—
tJ
Cycle-to-Cycle Output Jitter (Peak-to-Peak) at 133MHz
–75
Duty Cycle
45
tR
Output Rise Time for 3.3V Outputs (20% to 80%)
0.8
tF
Output Fall Time for 3.3V Outputs (20% to 80%)
0.8
tR
Output Rise Time for 2.5V Outputs (20% to 80%)
0.5
tF
Output Fall Time for 2.5V Outputs (20% to 80%)
0.5
Typ.
Max.
Unit
—
150
ps
—
50
ps
—
150
ps
—
150
ps
—
200
ps
—
75
ps
—
55
%
—
2.1
ns
—
2.1
ns
—
1.5
ns
—
1.5
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 5V2528A(1)
Symbol
Parameter(2)
Min.
tPHASE error
Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-166MHz)
–150
tPHASEerror-jitter(3) Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (166MHz)
–50
tSK1(0)(4)
Output Skew between 3.3V Outputs
—
tSK2(0)(4)
Output Skew between 2.5V Outputs
—
tSK3(0)(4,5)
Output Skew between 2.5V and 3.3V Outputs 25MHz to 133MHz
—
133MHz to 166MHz
—
tJ
Cycle-to-Cycle Output Jitter (Peak-to-Peak) at 166MHz
–75
Duty Cycle
45
tR
Output Rise Time for 3.3V Outputs (20% to 80%)
0.8
tF
Output Fall Time for 3.3V Outputs (20% to 80%)
0.8
tR
Output Rise Time for 2.5V Outputs (20% to 80%)
0.5
tF
Output Fall Time for 2.5V Outputs (20% to 80%)
0.5
Typ.
Max.
Unit
—
150
ps
—
50
ps
—
150
ps
—
150
ps
—
200
ps
—
250
—
75
ps
—
55
%
—
2.1
ns
—
2.1
ns
—
1.5
ns
—
1.5
ns
NOTES:
1. All parameters are measured with the following load conditions: 30pF || 500Ω for 3.3V outputs and 20pF || 500Ω for 2.5V outputs.
2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
3. Phase error does not include jitter.
4. All skew parameters are only valid for equal loading of all outputs.
5. Measured for VDDQ = 2.3V and 3V, 2.5V and 3.3V, or 2.7V and 3.6V.
5
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