IDT71V256SA10YGI8 データシートの表示（PDF） - Integrated Device Technology

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IDT71V256SA10YGI8

Lower Power 3.3V CMOS Fast SRAM 256K (32K x 8-Bit)

Integrated Device Technology 

IDT71V256SA

3.3V CMOS Static RAM 256K (32K x 8-Bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4,6)

t WC

ADDRESS

tOHZ (5)

OE

t AW

CS

t AS

tWP (6)

t WR

WE

DATAOUT

t WHZ (5)

(3)

t OW (5)

(3)

t DW

t DH

DATAIN

DATA VALID

, 3101 drw 09

NOTES:

1. A write occurs during the overlap of a LOW CS and a LOW WE.

2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

3. During this period, I/O pins are in the output state so that the input signals must not be applied.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the

spectified tWP.

Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,4)

t WC

ADDRESS

t AW

CS

tAS

WE

tCW (5)

tWR

t DW

t DH

DATAIN

DATA VALID

, 3101 drw 10

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the

spectified tWP.

6

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