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IDT71V424L データシートの表示(PDF) - Integrated Device Technology

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IDT71V424L
IDT
Integrated Device Technology IDT
IDT71V424L Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
3.3V CMOS Static RAM
4 Meg (512K x 8-Bit)
IDT71V424S
IDT71V424L
Features
512K x 8 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
— Commercial and Industrial: 10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
Functional Block Diagram
Description
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized
as 512K x 8. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V424 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V424 are TTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44-
pin, 400 mil TSOP.
A0
ADDRESS
DECODER
A18
4,194,304-BIT
MEMORY ARRAY
I/O0 - I/O7
WE
OE
CS
8
8
CONTROL
LOGIC
8
I/O CONTROL
3622 drw 01
1
©2004 Integrated Device Technology, Inc.
JULY 2004
DSC-3622/06

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