IDT72041 データシートの表示（PDF） - Integrated Device Technology
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IDT72041 Datasheet PDF : 14 Pages
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IDT72021, IDT72031, IDT72041
CMOS ASYNCHRONOUS FIFO WITH RETRANSMIT 1K x 9, 2K x 9, 4K x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Sta-
tus flags (EF, FF, HF, and AEF) can be detected from any one
device. Figure 14 demonstrates an 18-bit word width by using
two IDT72021/031/041 devices. Any word width can be at-
tained by adding additional IDT72021/031/041s.
18
DATA IN (D)
WRITE (W)
FULL FLAG (FF)
RESET (RS)
AEF HF
9
AEF HF
9
IDT
72021/031/041
9
IDT
72021/031/041
9
OUTPUT ENABLE (OE)
READ (R)
EMPTY FLAG (EF)
RETRANSMIT (RT)
XI
XI
18
DATA OUT (Q)
2677 drw 17
Figure 14. Block Diagram of 1K/2K/4K x 18 FIFO Memory Used in Width Expansion Configuration
NOTE:
1. Flag detection is accomplished by monitoring the FF, EF, HF and AEF signals on either (any) device used in the width expansion configuration. Do
not connect any output signals together.
DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT72021/031/041 can easily be adapted to applica-
tions when the requirements are for greater than 1K/2K/4K
words. Figure 15 demonstrates Depth Expansion using three
IDT72021/031/041s. Any depth can be attained by adding
additional devices. The IDT72021/031/041 operates in the
Depth Expansion configuration when the following conditions
are met:
1. The first device must be designed by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied
to the Expansion In (XI) pin of the next device. See
Figure 15.
4. External logic is needed to generate a composite Full
Flag (FF) and Empty Flag (EF). This requires the ORing
of all EFs and ORing of all FFs (i.e. all must be set to
generate the correct composite FF or EF). See
Figure 15.
5. The Retransmit (RT) function and Half-Full Flag (HF) are
not available in the Depth Expansion Mode. For addi-
tional information refer to Tech Note 9: “Cascading
FIFOs or FIFO Modules”.
COMPOUND EXPANSION MODE
The two expansion techniques described above can be
applied together in a straight forward manner to achieve large
FIFO arrays (see Figure 16).
BIDIRECTIONAL MODE
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT72021/031/041s as shown in
Figure 17. Care must be taken to assure that the appropriate
flag is monitored by each system (i.e., FF is monitored on the
device where W is used; EF is monitored on the device where
R is used). Both Depth Expansion and Width Expansion may
be used in this mode.
DATA FLOW-THROUGH MODES
Two types of flow-through modes are permitted: a read
flow-through and write flow-through mode. For the read flow-
through mode (Figure 18), the FIFO permits the reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge. It remains on the bus until
the R line is raised from LOW-to-HIGH, after which the bus
would go into a three-state mode after tRHZ ns. The EF line
would have a pulse showing temporary deassertion and then
would be asserted. In the interval of time that R was LOW,
more words can be written to the FIFO (the subsequent writes
after the first write edge will be deassert the Empty Flag);
however, the same word (written on the first write edge),
presented to the output bus as the read pointer, would not be
incremented when R was LOW. On toggling R, the other
words that are written to the FIFO will appear on the output bus
as in the read cycle timings.
5.09
11
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