IDT72421L50(1995) データシートの表示（PDF） - Integrated Device Technology

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IDT72421L50
(Rev.:1995)

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

WCLK

tCLKH

tCLK

tCLKL

D0 - D8

WEN1

tDS

DATA IN VALID

tENS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

tDH

tENH

NO OPERATION

WEN2/

(If Applicable)

FF

RCLK

tSKEW1(1)

tWFF

NO OPERATION

tWFF

REN1,

REN2

2655 drw 07

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between

the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.

Figure 5. Write Cycle Timing

5.07

10

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