IDT72421L15(1995) データシートの表示（PDF） - Integrated Device Technology

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IDT72421L15
(Rev.:1995)

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

WCLK

tDS

D0 - D8

WEN1

DATA WRITE 1

tENS

tENH

tENS

tENH

WEN2

(If Applicable)

RCLK

tSKEW1

tFRL(1)

tREF

EF

REN1,

REN2

MILITARY AND COMMERCIAL TEMPERATURE RANGES

tREF

tDS

DATA WRITE 2

tENS

tENH

tENS

tENH

tSKEW1

(1)

tFFL

tREF

OE

Q0 - Q8

LOW

tA

DATA IN OUTPUT REGISTER

DATA READ

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timings apply only at at the Empty Boundary (EF = LOW).

Figure 9. Empty Flag Timing

2655 drw 11

5.07

14

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