IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
tCLKH
tCLKL
(4)
WCLK
WEN1
tENS
tENH
WEN2
(If Applicable)
PAF
tENS
tENH
tPAF
(1)
Full - (m+1) words in FIFO
RCLK
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Full - m words in FIFO(2)
tSKEW2 (3)
tPAF
REN1,
REN2
tENS tENH
2655 drw 12
NOTES:
1. PAF offset = m.
2. 64 - m words in for IDT72421, 256 - m words in FIFO for IDT72201, 512 - m words for IDT72211, 1024 - m words for IDT72221, 2048 - m words for IDT72231,
4096 - m words for IDT72241.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.
Figure 10. Programmable Full Flag Timing
5.07
15