IDT72421L35(1995) データシートの表示（PDF） - Integrated Device Technology

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IDT72421L35
(Rev.:1995)

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING CONFIGURATIONS

SINGLE DEVICE CONFIGURATION - A single IDT72421/

72201/72211/72221/72231/72241 may be used when the

application requirements are for 64/256/512/1024/2048/4096

words or less. When the IDT72421/72201/72211/72221/

72231/72241 are in a Single Device Configuration, the Read

Enable 2 (REN2) control input can be grounded (see Figure

14). In this configuration, the Write Enable 2/Load (WEN2/LD)

pin is set LOW at Reset so that the pin operates as a control

to load and read the programmable flag offsets.

RESET (RS)

WRITE CLOCK (WCLK)

WRITE ENABLE 1 (WEN1)

WRITE ENABLE 2/LOAD (WEN2/LD)

DATA IN (D0 - D8)

FULL FLAG (FF)

PROGRAMMABLE ALMOST FULL (PAF)

IDT

72421/

72201/

72211/72221/

72231/

72241

READ CLOCK (RCLK)

READ ENABLE 1 (REN1)

OUTPUT ENABLE (OE)

DATA OUT (Q0 - Q8)

EMPTY FLAG (EF)

PROGRAMMABLE ALMOST EMPTY (PAE)

READ ENABLE 2 (REN2)

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Figure 14. Block Diagram of Single 64 x 9/256 x 9/512 x 9/1024 x 9/2048 x 9/4096 x 9 Synchronous FIFO

WIDTH EXPANSION CONFIGURATION - Word width may

be increased simply by connecting the corresponding input

controls signals of multiple devices. A composite flag should

be created for each of the end-point status flags (EF and FF).

The partial status flags (AE and AF) can be detected from any

one device. Figure 15 demonstrates a 18-bit word width by

using two IDT72421/72201/72211/72221/72231/72241s. Any

word width can be attained by adding additional IDT72421/

72201/72211/72221/72231/72241s.

When the IDT72421/72201/72211/72221/72231/72241 are

in a Width Expansion Configuration, the Read Enable 2

(REN2) control input can be grounded (see Figure 15). In this

configuration, the Write Enable 2/Load (WEN2/LD) pin is set

LOW at Reset so that the pin operates as a control to load and

read the programmable flag offsets.

RESET (RS)

DATA IN (D)

18

9

WRITE CLOCK (WCLK)

WRITE ENABLE1 (WEN1)

WRITE ENABLE2/LOAD (WEN2/LD)

FULL FLAG (FF) #1

FULL FLAG (FF) #2

PROGRAMMABLE (PAF)

IDT

72421/

72201/

72211/

72221/

72231/

72241

9

9

RESET (RS)

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

IDT

72421/

PROGRAMMABLE (PAE)

72201/

72211/

EMPTY FLAG (EF) #1

72221/ EMPTY FLAG (EF) #2

72231/

72241

9 DATA OUT (Q) 18

READ ENABLE 2 (REN2)

READ ENABLE 2 (REN2)

Figure 15. Block Diagram of 64 x 18/256 x 18/512 x 18/1024 x 18/2048 x 18/4096 x 18 Synchronous FIFO

Used in a Width Expansion Configuration

5.07

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