IDT72421L15(1995) データシートの表示（PDF） - Integrated Device Technology

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IDT72421L15
(Rev.:1995)

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

Com'l.

Commercial & Military

72421L12 72421L15

72201L12 72201L15

72211L12 72211L15

72421L20 72421L25 72421L35 72421L50

72201L20 72201L25 72201L35 72201L50

72211L20 72211L25 72211L35 72211L50

Symbol

Parameter

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

fS

Clock Cycle Frequency

— 83.3 — 66.7 — 50 — 40 — 28.6 — 20

tA

Data Access Time

2 8 2 10 2 12 3 15 3 20 3 25

tCLK

Clock Cycle Time

12 — 15 — 20 — 25 — 35 — 50 —

tCLKH Clock High Time

5 — 6 — 8 — 10 — 14 — 20 —

tCLKL Clock Low Time

5 — 6 — 8 — 10 — 14 — 20 —

tDS

Data Set-up Time

3 — 4 — 5 — 6 — 8 — 10 —

tDH

Data Hold Time

0 — 1 — 1 — 1 — 2 — 2—

tENS

Enable Set-up Time

3 — 4 — 5 — 6 — 8 — 10 —

tENH

Enable Hold Time

0 — 1 — 1 — 1 — 2 — 2—

tRS

Reset Pulse Width(1)

12 — 15 — 20 — 25 — 35 — 50 —

tRSS

Reset Set-up Time

12 — 15 — 20 — 25 — 35 — 50 —

tRSR Reset Recovery Time

12 — 15 — 20 — 25 — 35 — 50 —

tRSF

tOLZ

Reset to Flag and Output Time

— 12 — 15 — 20 — 25

Output Enable to Output in Low-Z(2) 0 — 0 — 0 — 0 —

— 35 — 50

0 — 0—

tOE

Output Enable to Output Valid

3 7 3 8 3 10 3 13 3 15 3 28

tOHZ

Output Enable to Output in High-Z(2) 3

7

3

8 3 10 3 13

3 15 3 28

tWFF Write Clock to Full Flag

— 8 — 10 — 12 — 15 — 20 — 30

tREF

Read Clock to Empty Flag

— 8 — 10 — 12 — 15 — 20 — 30

tAF

Write Clock to Almost-Full Flag

— 8 — 10 — 12 — 15 — 20 — 30

tAE

Read Clock to Almost-Empty Flag — 8 — 10 — 12 — 15 — 20 — 30

tSKEW1 Skew time between Read Clock & 5 — 6 — 8 — 10 — 12 — 15 —

Write Clock for Empty Flag &Full Flag

tSKEW2 Skew time between Read Clock & 22 — 28 — 35 — 40 —

Write Clock for Almost-Empty Flag &

Almost-Full Flag

42 — 45 —

NOTES:

1. Pulse widths less than minimum values are not allowed.

2. Values guaranteed by design, not currently tested.

Unit

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

2655 tbl 07

5.07

4

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