IDT72421L35(1995) データシートの表示（PDF） - Integrated Device Technology

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IDT72421L35
(Rev.:1995)

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

tRS

RS

tRSS

REN1,

REN2

tRSS

WEN1

tRSS

WEN2/LD (1)

tRSF

EF, PAE

tRSF

FF, PAF

Q0 - Q8

tRSF

MILITARY AND COMMERCIAL TEMPERATURE RANGES

tRSR

tRSR

tRSR

OE = 1 (2)

OE = 0

2655 drw 06

NOTES:

1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as

a load enable for the programmable flag offset registers.

2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.

3. The clocks (RCLK, WCLK) can be free-running during reset.

Figure 4. Reset Timing

5.07

9

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