IDT72421L10(2017) データシートの表示（PDF） - Integrated Device Technology

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IDT72421L10
(Rev.:2017)

CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

WCLK

D0 - D8

FF

WEN1

WEN2

(If Applicable)

NO WRITE

tSKEW1

tDS

tWFF

tENS

tENS

tWFF

tENH

tENH

NO WRITE

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

NO WRITE

tSKEW1

tWFF

tENS(1)

tENS(1)

RCLK

REN1,

tENS

REN2

OE LOW

tENH

tA

Q0 - Q8 DATA IN OUTPUT REGISTER

tENS

tENH

tA

DATA READ

NOTE:

1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.

Figure 8. Full Flag Timing

NEXT DATA READ

2655 drw 10

WCLK

tDS

D0 - D8

tENS

WEN1

tENS

WEN2

(If Applicable)

RCLK

DATA WRITE 1

tENH

tENH

tSKEW1

tFRL(1)

tREF

EF

tREF

tDS

tENS

DATA WRITE 2

tENH

tENS

tENH

tSKEW1

tFFL(1)

tREF

REN1,

REN2

OE LOW

tA

Q0 - Q8 DATA IN OUTPUT REGISTER

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK+ tSKEW1

The Latency Timings apply only at the Empty Boundary (EF = LOW).

Figure 9. Empty Flag Timing

©

10

DATA READ

2655 drw 11

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