IDT72421L10(2017) データシートの表示（PDF） - Integrated Device Technology
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IDT72421L10
(Rev.:2017)
(Rev.:2017)
Integrated Device Technology
IDT72421L10 Datasheet PDF : 14 Pages
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IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
The contents of the offset registers can be read on the output lines when the
Write Enable 2/Load (WEN2/LD) pin is set LOW and both Read Enables (REN1,
REN2) are set LOW. Data can be read on the LOW-to-HIGH transition of the
Read Clock (RCLK).
A read and write should not be performed simultaneously to the offset
registers.
IDT72421 - 64 x 9-BIT
8
65
0
Empty Offset (LSB) Reg.
Default Value 007H
8
0
8
65
0
Full Offset (LSB) Reg.
Default Value 007H
8
0
IDT72201 - 256 x 9-BIT
8
7
0
Empty Offset (LSB) Reg.
Default Value 007H
8
0
8
7
0
Full Offset (LSB) Reg.
Default Value 007H
8
0
IDT72211 - 512 x 9-BIT
8
7
0
Empty Offset (LSB)
Default Value 007H
8
1
0
(MSB)
0
8
7
0
Full Offset (LSB)
Default Value 007H
8
1
0
(MSB)
0
IDT72221 - 1,024 x 9-BIT
8
7
0
Empty Offset (LSB) Reg.
Default Value 007H
8
1
0
(MSB)
00
8
7
0
Full Offset (LSB) Reg.
Default Value 007H
8
1
0
(MSB)
00
IDT72231 - 2,048 x 9-BIT
8
7
0
Empty Offset (LSB) Reg.
Default Value 007H
8
2
0
(MSB)
000
8
7
0
Full Offset (LSB) Reg.
Default Value 007H
8
2
0
(MSB)
000
IDT72241 - 4,096 x 9-BIT
8
7
0
Empty Offset (LSB)
Default Value 007H
8
3
0
(MSB)
0000
8
7
0
Full Offset (LSB)
Default Value 007H
8
3
0
(MSB)
0000
IDT72251 8,192 x 9-BIT
8
7
0
Empty Offset (LSB)
Default Value 007H
8
4
0
(MSB)
00000
8
7
0
Full Offset (LSB)
Default Value 007H
8
4
0
(MSB)
00000
2655 drw 05
Figure 3. Offset Register Location and Default Values
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