IDT72421L10(2017) データシートの表示（PDF） - Integrated Device Technology

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IDT72421L10
(Rev.:2017)

CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RS

REN1, REN2

WEN1

tRS

tRSS

tRSS

tRSR

tRSR

WEN2/LD (1)

tRSS

tRSR

tRSF

EF, PAE

tRSF

FF, PAF

Q0 - Q8

tRSF

OE = 1 (2)

OE = 0

2655 drw 06

NOTES:

1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable

flag offset registers.

2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.

3. The clocks (RCLK, WCLK) can be free-running during reset.

Figure 4. Reset Timing

WCLK

D0 - D8

WEN1

WEN2/

(If Applicable)

FF

tSKEW1(1)

RCLK

tCLKH

tCLK

tCLKL

tDS

DATA IN VALID

tENS

tENS

tWFF

tDH

tENH

tENH

tWFF

NO OPERATION

NO OPERATION

REN1,

REN2

2655 drw 07

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK

and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

Figure 5. Write Cycle Timing

©

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