IDT72421L10(2017) データシートの表示（PDF） - Integrated Device Technology

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IDT72421L10
(Rev.:2017)

CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

RCLK

REN1,

REN2

EF

Q0 - Q8

OE

tENS

tCLKH

tCLK

tCLKL

tENH

NO OPERATION

tREF

tREF

tOLZ

tA

tOE

VALID DATA

tOHZ

tSKEW1(1)

WCLK

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WEN1

WEN2

2655 drw 08

NOTE:

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK

and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.

Figure 6. Read Cycle Timing

WCLK

tDS

D0 - D8

WEN1

WEN2

(If Applicable)

RCLK

D1

tENS

D0 (First Valid Write)

tENS

tSKEW1

tFRL (1)

tREF

EF

REN1,

REN2

tENS

tA

Q0 - Q8

tOLZ

tOE

OE

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timings apply only at the Empty Boundary (EF = LOW).

Figure 7. First Data Word Latency Timing

©

9

D2

D3

tA

D0

D1

2655 drw 09

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