IDT72200 データシートの表示（PDF） - Integrated Device Technology
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IDT72200
Integrated Device Technology
IDT72200 Datasheet PDF : 11 Pages
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IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
PIN CONFIGURATION
COMMERCIAL TEMPERATURE RANGE
D4 1
28 D5
D3 2
27 D6
D2 3
D1 4
D0 5
AF 6
AE 7
26 D7
25
RS
24
WEN
23 WCLK
22 VCC
GND 8
21 Q7
RCLK 9
REN 10
OE 11
EF 12
FF 13
Q0 14
20 Q6
19 Q5
18 Q4
17 Q3
16 Q2
15 Q1
2680 drw02
PLASTIC THIN DIP (P28-2, order code: TP)
TOP VIEW
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
D0 - D7
Data Inputs
I Data inputs for a 8-bit bus.
RS
Reset
I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and AF go
HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLK
Write Clock
I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted.
WEN
Write Enable
I When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written
into the FIFO if the FF is LOW.
Q0 - Q7 Data Outputs
O Data outputs for a 8-bit bus.
RCLK
Read Clock
I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted.
REN
Read Enable
I When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from
the FIFO if the EF is LOW.
OE
Output Enable
I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
EF
Empty Flag
O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO
is not empty. EF is synchronized to RCLK.
AE
Almost-Empty Flag O When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized to RCLK.
AF
Almost-Full Flag O When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to WCLK.
FF
Full Flag
O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not
full. FF is synchronized to WCLK.
VCC
Power
One +5 volt power supply pin.
GND
Ground
One 0 volt ground pin.
2
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