IDT72200 データシートの表示（PDF） - Integrated Device Technology

部品番号

コンポーネント説明

メーカー

IDT72200

CMOS SyncFIFO™ 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8

Integrated Device Technology 

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™

64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8

RS

REN

WEN

EF, AE

FF, AF

Q0 - Q7

tRS

tRSS

tRSS

tRSF

tRSF

tRSF

NOTES:

1. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.

2. The Clocks (RCLK, WCLK) can be free-running during reset.

COMMERCIAL TEMPERATURE RANGE

tRSR

tRSR

OE = 1(1)

OE = 0

2680 drw 04

Figure 2. Reset Timing

WCLK

D0 - D7

WEN

FF

RCLK

tCLKH

tCLK

tCLKL

tDS

DATA IN VALID

tENS

tWFF

tSKEW1(1)

tDH

tENH

tWFF

NO OPERATION

REN

2680 drw 05

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the

rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

Figure 3. Write Cycle Timing

6

Share Link: