IDT72200 データシートの表示（PDF） - Integrated Device Technology

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IDT72200

CMOS SyncFIFO™ 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8

Integrated Device Technology 

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™

64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8

RCLK

tENS

REN

EF

Q0 - Q7

OE

tCLKH

tCLK

tCLKL

tENH

tREF

NO OPERATION

tOLZ

tA

tOE

WCLK

COMMERCIAL TEMPERATURE RANGE

tREF

VALID DATA

tOHZ

tSKEW1 (1)

WEN

NOTE:

2680 drw 06

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of WCLK and the

rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.

Figure 4. Read Cycle Timing

WCLK

D0 - D7

tDS

D0 (first valid write)

D1

WEN

RCLK

EF

tENS

tSKEW1

(1)

tFRL

tREF

REN

tENS

tA

Q0 - Q7

OE

tOLZ

tOE

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timing apply only at the Empty Boundary (EF = LOW).

Figure 5. First Data Word Latency Timing

7

D2

tA

D0

D3

D1

2680 drw 07

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