IDT72200 データシートの表示（PDF） - Integrated Device Technology

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IDT72200

CMOS SyncFIFO™ 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8

Integrated Device Technology 

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™

64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8

WCLK

D0 - D7

FF

WEN

NO WRITE

tSKEW1

tDS

tWFF

DATA WRITE

tWFF

tENS

COMMERCIAL TEMPERATURE RANGE

NO WRITE

NO WRITE

tSKEW1

tWFF

tENS

RCLK

REN

tENS

OE LOW

tENH

tA

tENS

tENH

tA

Q0 - Q7 DATA IN OUTPUT REGISTER

DATA READ

Figure 6. Full Flag Timing

NEXT DATA READ

2680 drw 08

WCLK

tDS

D0 - D7

tENS

WEN

RCLK

EF

DATA WRITE 1

tENH

tSKEW1

tFRL (1)

tREF

tREF

tDS

tENS

DATA WRITE 2

tENH

tSKEW1

tFRL (1)

tREF

REN

OE LOW

Q0 - Q7

tA

DATA IN OUTPUT REGISTER

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timing apply only at the Empty Boundary (EF = LOW).

Figure 7. Empty Flag Timing

8

DATA READ

2680 drw 09

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