IDT723631 データシートの表示（PDF） - Integrated Device Technology
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IDT723631 Datasheet PDF : 23 Pages
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IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTION
RESET
The IDT723631/723641/723651 is reset by taking the
reset (RST) input LOW for at least four port-A clock (CLKA)
and four port-B (CLKB) LOW-to-HIGH transitions. The reset
input may switch asynchronously to the clocks. A reset
initializes the memory read and write pointers and forces the
input-ready (IR) flag LOW, the output-ready (OR) flag LOW,
the almost-empty (AE) flag LOW, and the almost-full (AF) flag
HIGH. Resetting the device also forces the mailbox flags
(MBF1, MBF2) HIGH. After a FIFO is reset, its input-ready flag
is set HIGH after at least two clock cycles to begin normal
operation. A FIFO must be reset after power up before data
is written to its memory.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFF-
SET PROGRAMMING
Two registers in the IDT723631/723641/723651 are used
to hold the offset values for the almost-empty and almost full
flags. The almost-empty (AE) flag offset register is labeled X,
and the almost-full (AF) flag offset register is labeled Y. The
offset register can be loaded with a value in three ways: one
of two preset values are loaded into the offset registers,
parallel load from port A, or serial load. The offset register
programming mode is chosen by the flag select (FS1, FS0)
inputs during a LOW-to-HIGH transition on the RST input (See
Table 1).
PRESET VALUES
If the preset value of 8 or 64 is chosen by the FS1 and FS0
inputs at the time of a RST LOW-to-HIGH transition according
to Table 1, the preset value is automatically loaded into the X
and Y registers. No other device initialization is necessary to
begin normal operation, and the IR flag is set HIGH after two
LOW-to-HIGH transitions on CLKA.
PARALLEL LOAD FROM PORT A
To program the X and Y registers from port A, the device
is reset with FS0 and FS1 LOW during the LOW-to-HIGH
transition of RST. After this reset is complete, the IR flag is set
HIGH after two LOW-to-HIGH transitions on CLKA. The first
two writes to the FIFO do not store data in its memory but load
the offset registers in the order Y, X. Each offset register of the
IDT723631, IDT723641, and IDT723651 uses port-A inputs
(A8-A0), (A9-A0), and (A10-A0), respectively. The highest
number input is used as the most significant bit of the binary
number in each case. Each register value can be pro-
grammed from 1 to 508 (IDT723631), 1 to 1020 (IDT723641),
and 1 to 2044 (IDT723651). After both offset registers are
programmed from port A, subsequent FIFO writes store data
in the SRAM.
SERIAL LOAD
To program the X and Y registers serially, the device is
reset with FS0/SD and FS1/SEN HIGH during the LOW-to-
HIGH transition of RST. After this reset is complete, the X and
Y register values are loaded bitwise through the FS0/SD input
on each LOW-to-HIGH transition of CLKA that the FS1/SEN
input is LOW. Eighteen-, 20-, or 22-bit writes are needed to
complete the programming for the IDT723631, IDT723641, or
IDT723651, respectively. The first-bit write stores the most
significant bit of the Y register, and the last-bit write stores the
least significant bit of the X register. Each register value can
be programmed from 1 to 508 (IDT723631), 1 to 1020
(IDT723641), or 1 to 2044 (IDT723651).
When the option to program the offset registers serially is
chosen, the input-ready (IR) flag remains LOW until all regis-
ter bits are written. The IR flag is set HIGH by the LOW-to-
HIGH transition of CLKA after the last bit is loaded to allow
normal FIFO operation.
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled
by the port-A chip select (CSA) and the port-A write/read
select (W/RA). The A0-A35 outputs are in the high-imped-
ance state when either CSA or W/RA is HIGH. The A0-A35
outputs are active when both CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a
LOW-to-HIGH transition of CLKA when CSA and the port-A
mailbox select (MBA) are LOW, W/RA, the port-A enable
(ENA), and the input-ready (IR) flag are HIGH (see Table 2).
Writes to the FIFO are independent of any concurrent FIFO
read.
The port-B control signals are identical to those of port-A
with the exception that the port-B write/read select (W/RB) is
the inverse of the port-A write/read select (W/RA). The state
of the port-B data (B0-B35) outputs is controlled by the port-
B chip select (CSB) and the port-B write/read select (W/RB).
The B0-B35 outputs are in the high-impedance state when
either CSB is HIGH or W/RB is LOW. The B0-B35 outputs are
active when CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to its output register on a LOW-
to-HIGH transition of CLKB when CSB and the port-B mailbox
select (MBB) are LOW, W/RB, the port-B enable (ENB), and
the output-ready (OR) flag are HIGH (see Table 3). Reads
from the FIFO are independent of any concurrent FIFO writes.
The setup- and hold-time constraints to the port clocks for
the port-chip selects and write/read selects are only for
enabling write and read operations and are not related to high-
FS1
FS0 RST
X and Y Registers (1)
H
H
↑
Serial Load
H
L
↑
64
L
H
↑
8
L
L
↑
Parallel Load From Port A
3023 tbl 08
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
Table 1. Flag Programming
9
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