IDT72T3655L7BBI データシートの表示（PDF） - Integrated Device Technology

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IDT72T3655L7BBI

2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

Integrated Device Technology 

IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync 36-BIT FIFO

1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36

PARTIAL RESET (PRS) MASTER RESET (MRS)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WRITE CLOCK (WCLK/WR)

WRITE ENABLE (WEN)

WRITE CHIP SELECT (WCS)

LOAD (LD)

(x36, x18, x9) DATA IN (D0 - Dn)

SERIAL CLOCK (SCLK)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

IDT

72T3645

72T3655

72T3665

72T3675

72T3685

72T3695

72T36105

72T36115

72T36125

READ CLOCK (RCLK/RD)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

READ CHIP SELECT (RCS)

(x36, x18, x9) DATA OUT (Q0 - Qn)

RCLK ECHO, ERCLK

REN ECHO, EREN

MARK

RETRANSMIT (RT)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)

HALF-FULL FLAG (HF)

BIG-ENDIAN/LITTLE-ENDIAN (BE)

INTERSPERSED/

NON-INTERSPERSED PARITY (IP)

INPUT WIDTH (IW) BUS- OUTPUT WIDTH (OW)

MATCHING

(BM)

5907 drw03

Figure 1. Single Device Configuration Signal Flow Diagram

TABLE 1 — BUS-MATCHING CONFIGURATION MODES

BM

IW

OW

Write Port Width

L

L

L

x36

H

L

L

x36

H

L

H

x36

H

H

L

x18

H

H

H

x9

NOTE:

1. Pin status during Master Reset.

Read Port Width

x36

x18

x9

x36

x36

6

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