IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant)
Symbol
Parameter
IDT72V3682L10
IDT72V3692L10
IDT72V36102L10
Min.
Max.
IDT72V3682L15
IDT72V3692L15
IDT72V36102L15
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
—
100
—
66.7
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
10
—
15
—
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
4.5
—
6
—
ns
tCLKL
Pulse Duration, CLKA and CLKB LOW
4.5
—
6
—
ns
tDS
Setup Time, A0-A35 before CLKA↑ and B0-B35
before CLKB↑
tENS1
Setup Time, CSA and W/RA, before
CLKA↑; CSB, and W/RB before CLKB↑
3
—
4
—
ns
4
—
4.5
—
ns
tENS2
tRSTS
Setup Time, ENA and MBA, before
CLKA↑; ENB, and MBB before CLKB↑
Setup Time, RST1 or RST2 LOW before CLKA↑
or CLKB↑(1)
3
—
4.5
—
ns
5
—
5
—
ns
tFSS
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
7.5
—
7.5
—
ns
tFWS
Setup Time, FWFT before CLKA↑
0
—
0
—
ns
tDH
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
0.5
—
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;
CSB, W/RB, ENB, and MBB after CLKB↑
0.5
—
tRSTH
Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑(1)
4
—
tFSH
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
2
—
1
—
ns
1
—
ns
4
—
ns
2
—
ns
tSKEW1(2) Skew Time, between CLKA↑ and CLKB↑ for EFA/ORA,
EFB/ORB, FFA/IRA, and FFB/IRB
7.5
—
7.5
—
ns
tSKEW2(2,3) Skew Time, between CLKA↑ and CLKB↑ for AEA,
AEB, AFA, and AFB
12
—
12
—
ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
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