IDT79R3052-20J(2001) データシートの表示（PDF） - Integrated Device Technology

部品番号

コンポーネント説明

メーカー

IDT79R3052-20J
(Rev.:2001)

RISControllers

Integrated Device Technology 

IDT79R3051/79R3052 INTEGRATED RISControllers

COMMERCIAL TEMPERATURE RANGE

INTRODUCTION

The IDT IDT79R3051 family is a series of high-perfor-

mance 32-bit microprocessors featuring a high level of inte-

gration which are targeted to high-performance, but cost-

sensitive embedded processing applications. The IDT79R3051

family is designed to bring the high-performance inherent in

the MIPS RISC architecture into low-cost, simplified, power-

sensitive applications.

Functional units were integrated onto the CPU core in order

to reduce the total system cost, without significantly degrading

system performance. Thus, the IDT79R3051 family is able to

offer 35MIPS of integer performance at 40MHz without requir-

ing external SRAM or caches.

Furthermore, the IDT79R3051 family brings dramatic power

reduction to these embedded applications, allowing the use of

low-cost packaging for devices up to 25 MHz. The IDT79R3051

family allows customer applications to bring maximum per-

formance at minimum cost.

Figure 1 shows a block-level representation of the func-

tional units within the IDT79R3051 family. The IDT79R3051

family could be viewed as the embodiment of a discrete

solution built around the IDT79R3000A or IDT79R3001.

However, by integrating this functionality on a single chip,

dramatic cost and power reductions are achieved.

Currently, there are four members of the IDT79R3051

family. All devices are pin- and software-compatible: the

differences lie in the amount of instruction cache, and in the

memory management capabilities of the processor:

• The IDT79R3052"E” incorporates 8kB of Instruction Cache,

and features a full-function Memory Management Unit

(MMU), including a 64-entry fully-associative Translation

Lookaside Buffer (TLB). This is the same MMU incorporated

into the IDT79R3000A and IDT79R3001.

• The IDT79R3052 also incorporates 8kB of Instruction Cache.

However, the MMU is a much simpler subset of the capabili-

ties of the enhanced versions of the architecture, and in fact

does not use a TLB.

• The IDT79R3051"E” incorporates 4KB of Instruction Cache.

Additionally, this device features the same full-function

MMU (including TLB file) as the IDT79R3052"E”, and

IDT79R3000A.

• The IDT79R3051 incorporates 4KB of Instruction Cache,

and uses the simpler memory management model of the

IDT79R3052.

An overview of the functional blocks incorporated in these

devices follows.

CPU Core

The CPU core is a full 32-bit RISC integer execution

engine, capable of sustaining close-to single cycle execution

rate. The CPU core contains a five stage pipeline and 32

orthogonal 32-bit registers. The IDT79R3051 family imple-

ments the MIPS ISA. In fact, the execution engine of the

IDT79R3051 family is the same as the execution engine of the

IDT79R3000A (and IDT79R3001). Thus the IDT79R3051

family is binary-compatible with those CPU engines.

The execution engine of the IDT79R3051 family uses a

five-stage pipeline to achieve close-to single cycle execution.

A new instruction can be started in every clock cycle; the

execution engine actually processes five instructions con-

currently (in various pipeline stages). Figure 2 shows the

concurrency achieved by the IDT79R3051 family pipeline.

I#1 IF RD ALU MEM WB

I#2 IF RD ALU MEM WB

I#3 IF RD ALU MEM WB

I#4 IF RD ALU MEM WB

I#5 IF RD ALU MEM WB

Current

CPU

Cycle

2874 drw 02

Figure 2. R3051 Family 5-Stage Pipeline

System Control Co-Processor

The R3051 family also integrates on-chip the System

Control Co-processor, CP0. CP0 manages both the excep-

tion handling capability of the IDT79R3051 family, as well as

the virtual to physical mapping of the IDT79R3051 family.

There are two versions of the IDT79R3051 family architec-

ture: the Extended Architecture Versions (the IDT79R3051E

and IDT79R3052E) contain a fully associative 64-entry TLB

which maps 4KB virtual pages into the physical address

space. The virtual to physical mapping thus includes kernel

segments which are hard mapped to physical addresses, and

kernel and user segments which are mapped on a page basis

by the TLB into anywhere within the 4GB physical address

space. In this TLB, 8-page translations can be “locked” by the

kernel to insure deterministic response in real-time applica-

tions. These versions thus use the same MMU structure as

that found in the IDT79R3000A and IDT79R3001. Figure 3

shows the virtual-to-physical address mapping found in the

Extended Architecture versions of the processor family.

The Extended Architecture devices allow the system

designer to implement kernel software to dynamically manage

User task utilization of memory resources, and also allow the

Kernel to effectively “protect” certain resources from user

tasks. These capabilities are important in a number of

embedded applications, from process control (where resource

protection may be extremely important) to X-Window display

systems (where virtual memory management is extremely

important), and can also be used to simplify system debugging.

5.3

2

Share Link: