IDT79R3052-20J(2001) データシートの表示（PDF） - Integrated Device Technology
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IDT79R3052-20J Datasheet PDF : 26 Pages
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IDT79R3051/79R3052 INTEGRATED RISControllers
PERFORMANCE OVERVIEW
The IDT79R3051 family achieves a very high level of per-
formance. This performance is based on:
• An efficient execution engine. The CPU performs ALU
operations and store operations at a single cycle rate, and has
an effective load time of 1.3 cycles, and a branch execution
rate of 1.5 cycles (based on the ability of the compilers to
avoid software interlocks). Thus, the execution engine
achieves over 35MIPS performance when operating out of
cache.
• Large on-chip caches. The IDT79R3051 family contains
caches which are substantially larger than those on the major-
ity of today’s embedded microprocessors. These large caches
minimize the number of bus transactions required, and allow
the R3051 family to achieve actual sustained performance,
very close to its peak execution rate.
• Autonomous multiply and divide operations. The
IDT79R3051 family features an on-chip integer multiplier/
divide unit which is separate from the other ALU. This allows
the IDT79R3051 family to perform multiply or divide opera-
tions in parallel with other integer operations, using a single
multiply or divide instruction rather than “step” operations.
• Integrated write buffer. The IDT79R3051 family features a
four-deep write buffer, which captures store target ad-dresses
and data at the processor execution rate and retires it to main
memory at the slower main memory access rate. Use of on-
chip write buffers eliminates the need for the processor to stall
when performing store operations.
• Burst read support. The IDT79R3051 family enables the
system designer to utilize page mode or nibble mode RAMs
when performing read operations to minimize the main mem-
ory read penalty and increase the effective cache hit rates.
These techniques combine to allow the processor to
achieve 35MIPS integer performance, and over 64,000 dhrys-
tones at 40MHz without the use of external caches or zero
wait-state memory devices.
SELECTABLE FEATURES
The IDT79R3051 family allows the system designer to con-
figure some aspects of operation. These aspects are estab-
lished when the device is reset and include:
• Big Endian vs. Little Endian operation: The part can be
configured to operate with either byte ordering convention,
and in fact may also be dynamically switched between the two
conventions. This facilitates the porting of applications from
other processor architectures, and also permits inter-commu-
nications between various types of processors and databases.
• Data cache refill of one or four words: The memory sys-
tem must be capable of performing 4-word transfers to satisfy
cache misses. This option allows the system designer to
choose between one- and four-word refill on data cache
misses, depending on the performance each option brings to
his application.
COMMERICAL TEMPERATURE RANGE
THERMAL CONSIDERATIONS
The IDT79R3051 family utilizes special packaging tech-
niques to improve the thermal properties of high-speed pro-
cessors. Thus, all versions of the IDT79R3051 family are
packaged in cavity-down packaging.
The lowest cost members of the family use a standard cav-
ity-down, injection molded PLCC package (the "J" package).
This package, coupled with the power reduction techniques
employed in the design of the IDT79R3051 family, allows
operation at speeds to 25MHz. However, at higher speeds,
additional thermal care must be taken.
For this reason, the IDT79R3051 family is also available in
the DL84 plastic package, with the die being attached to a
heat slug. The DL84 allows for more efficient thermal transfer
between the die and the heat slug. The heat slug offers a
greater area for convection and conduction to the PCB at any
given temperature. Even nominal amounts of airflow will dra-
matically reduce the junction temperature of the die, resulting
in cooler operation. The DL84 package is available at 35/
40MHz frequencies, and is pin- and form-compatible with the
PLCC package. Thus, designers can choose to utilize this
package without changing their PCB.
The members of the IDT79R3051 family are guaranteed in
a case temperature range of 0°C to +85°C. The type of pack-
age, speed (power) of the device, and airflow conditions affect
the equivalent ambient conditions which meet this specifica-
tion.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(ØCA) of the given package. The following equation relates
ambient and case temperature:
TA = TC - P * ØCA
where P is the maximum power consumption at hot tempera-
ture, calculated by using the maximum ICC specification for
the device.
Typical values for ØCA at various airflows are shown in
Table 1 for the various packages.
Airflow (m/s) 0
1
2
3
4
5
DL84 ØJA
DL84 ØCA
PL84 ØJA
PL84 ØCA
21.0 12.8 12.0 9.9 9.2 8.5
18.3 10.1 9.3 7.2 6.6 5.8
36.6 29.6 27.0 26.2 25.4 24.8
18.3 10.1 9.3 7.2 6.6 5.8
Table 1 Thermal Resistance at Various Airflows
5.3
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