IDT821054A データシートの表示（PDF） - Integrated Device Technology

部品番号

コンポーネント説明

メーカー

IDT821054A

QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

Integrated Device Technology 

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

INDUSTRIAL TEMPERATURE

2.1.2 PCM BUS

The IDT821054A provides two flexible PCM buses for all 4 channels.

The digital PCM data can be compressed (A/µ-law) or linear code. As

shown in Figure - 3, the data rate can be configured as same as the Bit

Clock (BCLK) or half of it. The PCM data is transmitted or received

either on the rising edges or on the falling edges of the BCLK signal. The

transmit and receive time slots can offset from the FS signal by 0 to 7

periods of BCLK. All these configurations are made by global register

GREG7, which is effective for all four channels.

The PCM data of each channel can be assigned to any time slot of

the PCM bus. The number of available time slots is determined by the

frequency of the BCLK signal. For example, if the frequency is 512 kHz,

8 time slots (TS0 to TS7) are available. If the frequency is 1.024 MHz,

16 time slots (TS0 to TS15) are available. The IDT821054A accepts

BCLK frequency of 512 kHz to 8.192 MHz at increments of 64 kHz.

When compressed PCM code (8-bit wide) is selected, the voice data

of one channel occupies one time slot. The TT[6:0] bits in local register

LREG5 select the transmit time slot for each channel, while the RT[6:0]

bits in LREG6 select the receive time slot for each channel.

When linear PCM code is selected, the voice data is a 16-bit 2’s

complement number (b13 to b0 are effective bits, b15 and b14 are as

same as the sign bit b13). So, the voice data of one channel occupies

one time slot group, which consists of 2 adjacent time slots. The TT[6:0]

bits in LREG5 select a transmit time slot group for the specified channel.

If TT[6:0] = n(d), it means that time slots TS(2n+1) and TS(2n+2) are

selected. For example, if TT[6:0] = 00H, it means that TS0 and TS1 are

selected. The RT[6:0] bits in LREG6 select a receive time slot group for

the specified channel in the same way.

The PCM data of each individual channel can be clocked out to

transmit PCM highway one (DX1) or two (DX2) on the programmed

edges of BCLK according to time slot assignment. The transmit PCM

highway is selected by the THS bit in LREG5. The frame sync (FS)

pulse identifies the beginning of a transmit frame (TS0). The PCM data

is serially transmitted on DX1 or DX2 with MSB first.

The PCM data of each individual channel is received from receive

PCM highway one (DR1) or two (DR2) on the programmed edges of

BCLK according to time slot assignment. The receive PCM highway is

selected by the RHS bit in LREG6. The frame sync (FS) pulse identifies

the beginning of a receive frame (TS0). The PCM data is serially

received from DR1 or DR2 with MSB first.

FS

BCLK

Single Clock

Transmit

Receive

PCM Clock Slope Bits

in GREG7:

CS = 000

CS = 001

CS = 010

Bit 7

TS0

BCLK

Double Clock

CS = 011

CS = 100

CS = 101

CS = 110

CS = 111

Figure - 3 Sampling Edge Selection Waveform

10

Share Link: