IDT82V1671 データシートの表示（PDF） - Integrated Device Technology
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IDT82V1671
Integrated Device Technology
IDT82V1671 Datasheet PDF : 107 Pages
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RSLIC (IDT82V1671) & CODEC (IDT82V1074) CHIPSET
INDUSTRIAL TEMPERATURE RANGE
2
PIN DESCRIPTIONS
2.1
RSLIC PIN DESCRIPTION
Name
VBH
RIS
BGND
TIS
VDD
AGND
CF
VCM
ACN
ACP
DCN
DCP
VTAC
CA
VTDC
VL
CB
M3
M2
M1
CS
RT
RSN
RSP
VCMB
RING
TIP
VBL
Type
Power
−
Power
−
Power
Power
Ο
I
I
I
I
I
O
−
O
O
−
I/O
I
I
I
O
I
I
O
I/O
I/O
Power
Pin Number
Description
1
Negative battery supply (−70 V ≤ VBH ≤ −52 V)
2
Ring sense, connected to the RING pin through an external resistor RS. Refer to “8 Application Circuits” on page 104
for details.
3
Battery ground. This pin should be externally connected to AGND.
4
Tip sense, connected to the TIP pin through an external resistor RS.
5
+3.3 V power supply.
6
Analog ground. This pin should be externally connected to BGND.
7
Output voltage of VBAT/2 (VBAT represents the selected battery voltage VBH or VBL). An external capacitor is
connected between this pin and the ground for filtering.
8
Reference voltage input, typical 1.5 V.
9
Differential AC voltage, negative.
10
Differential AC voltage, positive.
11
Differential DC voltage, negative.
12
Differential DC voltage, positive.
13
Sense transversal AC voltage.
14
External capacitor connection. An external capacitor is connected between this pin and the CB pin to separate the DC
component from the sense transversal voltage.
15
Sense transversal DC voltage.
16
Sense longitudinal voltage.
17
External capacitor connection. An external capacitor is connected between this pin and the CA pin to separate the DC
component from the sense transversal voltage.
18
Mode control input 3 or temperature information output.
The logic level of the CS pin determines the direction of the M3 pin. See the description of the CS pin for details.
19
Mode control input 2. This is a binary logic pin, together with M1 and M3, controlling the operating mode of the RSLIC.
20
Mode control input 1. This is a binary logic pin, together with M2 and M3, controlling the operating mode of the RSLIC.
Chip select input. It is a ternary logic pin.
When the CS pin is logic 0 (0 V< CS < 0.8 V), the RSLIC receives the mode control data from the CODEC through
the M1 to M3 pins.
21
When the CS pin is logic 1 (2.2 V< CS < 3.3 V), the RSLIC sends the temperature information of itself to the
CODEC through the M3 pin.
When the CS pin is 1.5 V (with ±0.5 V tolerance), the RSLIC neither receives the data from the CODEC nor sends
temperature information to it.
22
Ring trip operational amplifier output.
23
Negative ring trip operational amplifier input.
24
Positive ring trip operational amplifier input.
25
VCM buffer output, 1.5 V, used for external ringing mode.
26
Subscriber loop connection Ring.
27
Subscriber loop connection Tip.
28
Negative battery supply (−52 V ≤ VBL ≤ −20 V).
11
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