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IDTCV140 データシートの表示(PDF) - Integrated Device Technology

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IDTCV140
IDT
Integrated Device Technology IDT
IDTCV140 Datasheet PDF : 26 Pages
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IDTCV140
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
BYTE 4
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
Reserved
DOT96T
Reserved
PCIF1
PCIF0
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
Description / Function
0
DOT96 power down drive mode Driven in power down
Allow controlled by
PCI_STOP# assertion
Allow control of CPU_2
with assertion of CPU_STOP#
Allow control of CPU_1
with assertion of CPU_STOP#
Allow control of CPU_0
with assertion of CPU_STOP#
Free running, not
affected by PCI_STOP#
Free running, not
affected by CPU_STOP#
Free running, not
affected by CPU_STOP#
Free running, not
affected by CPU_STOP#
COMMERCIAL TEMPERATURE RANGE
1
Tristate
Stopped with
PCI_STOP#
Stopped with
CPU_STOP#
Stopped with
CPU_STOP#
Stopped with
CPU_STOP#
Type
Power On
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
1
RW
1
BYTE 5
Bit
7
6
5
4
3
2
1
0
Output(s) Affected
Description / Function
0
1
Type
SRCTs
SRCT PCI_STOP drive mode Driven in PCI_STOP Tristatewhenstopped
RW
CPUT2
CPUT2 CPU_STOP drive mode Driven in CPU_STOP# Tristatewhenstopped
RW
CPUT1
CPUT1 CPU_STOP drive mode Driven in CPU_STOP# Tristatewhenstopped
RW
CPUT0
CPUT0 CPU_STOP drive mode Driven in CPU_STOP# Tristatewhenstopped
RW
SRCs
CPUT2
SRCT PWRDWN drive mode
CPUT2 PWRDWN drive mode
Driven in power down Tristate in power down RW
Driven in power down Tristate in power down RW
CPUT1
CPUT1 PWRDWN drive mode
Driven in power down Tristate in power down RW
CPUT0
CPUT0 PWRDWN drive mode
Driven in power down Tristate in power down RW
Power On
0
0
0
0
0
0
0
0
BYTE 6
Bit
Output(s) Affected
Description / Function
0
1
Type
7
Only valid when Byte6 bit6 is 1
Hi-Z
REF/N mode
RW
6
Test Mode entry control
Normal operation
Test mode, controlled
RW
by byte 6 bit 7
5
Reserved
RW
4
REF Str1
REF drive strength
1x drive
2x drive
RW
Software PCI_STOP
Stop all PCI/F & SRC
3
Software PCI_STOP control for PCI, free running SRC
except PCIF[2:0]
normal
RW
function
and free running PCIF CLK.
and SRC clocks
(see PCI_Stop# table)
set to free running
2
FSC latched value on power up
R
1
FSB latched value on power up
R
0
FSA latched value on power up
R
Power On
0
0
0
1
1
7

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